Abstract: A multimedia controller apparatus provides for computer programmed volume control and summing of audio signals in an enhanced multimedia environment. The apparatus is capable of receiving and processing inputs from a CD-ROM FM synthesizer, general MIDI audio, microphone, PCM sampled sound, and telephony systems. From these inputs, it produces outputs for PCM sampled sound, telephony systems, and stereo line-out. Additionally, it provides for the integration of telephonic support functions into a multimedia system. The multimedia controller apparatus comprises a volume control portion for receiving and controlling the volume of a plurality of analog input signals. The volume controlled input signals are then combined by an aggregation portion. A telephony processing portion is also provided for processing the telephony input signals. Stereo outputs, mono outputs, digital samplable outputs, and telephony outputs can be formed from the combined analog and telephony signals by an output portion.

Abstract: A logic compiler wherein verification of a generated circuit model is performed automatically by comparing the operation of the circuit model with that of a corresponding mathematical behavior model. A novel user interface and circuit model generation means enables the user to obtain, in real time, performance specifications on the circuit selected by the user as well as incurring other benefits.

Abstract: A periodic sequence of signals is intiated and provided to a counter. During this time, a pulse (PULSE) is generated. Upon reaching a terminal count the pulse is terminated. The pulse is provided to a delay element which receives at its input a signal (s) entering, processed within or exiting a semiconductor device. The pulse and periodic sequence of signals are initiated by an edge detector detecting a trigger signal (TRIGGER), which may be the signal (s) being delayed. The sequence of signals is generated by a circuit element, such as a ring oscillator, and the periodicity of the sequence of signals is related to the inherent switching speed of the semiconductor device technology. A plurality of delay circuits are provided in a semiconductor device for individually delaying a plurality of signals entering, processed within and exiting the device. A library of delay circuits may pre-designed, and stored for implementation, as needed, in semiconductor devices.

Abstract: An adder array for adding two or more input addends, whose bit lengths are not necessarily matched, and a method of configuring the adder array are disclosed. The addends are organized according to bit weight, and bits of equal weight are added in adder columns. Carry-outs are introduced into subsequent, higher weight adder columns according to delay. Thereby, the delay associated with the addition of the addends is minimized. Method and apparatus is disclosed.

Abstract: An electrical connector having a generally cubical housing with a matchable cover, a plurality of plug-in receptacles disposed within the housing, plug-in openings provided on the surfaces of both the housing and the cover while the cover openings are mounted with slidable door each having at least one slot to selectively expose or cover-up the pairs of spaced-apart electrical contact strips embedded in the housing to render the receptacles accessible or to close them.