Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.

Abstract: A source driver, including a plurality of channel circuits, each of the plurality of channel circuits including a first digital-to-analog converter (DAC), a second DAC, a first switch, a second switch and an output buffer circuit, is provided. The output terminal of the output buffer circuit is configured to be coupled to a data line of a display panel. An output terminal of the first DAC is coupled to a first input terminal among the input terminals of the output buffer circuit. An output terminal of the second DAC is coupled to a second input terminal among the input terminals of the output buffer circuit. The first switch is disposed along a first signal path between the output terminal of the first DAC and the output terminal of the output buffer circuit. The second switch is disposed along a second signal path between the output terminal of the second DAC and the output terminal of the output buffer circuit.

Abstract: Provided is a semiconductor device includes a gate electrode, a gate dielectric layer, a channel layer, an insulating layer, a first source/drain electrode and a second source/drain electrode, a second dielectric layer, and a stop segment. The gate electrode is located within a first dielectric layer that overlies a substrate. The gate dielectric layer is located over the gate electrode. The channel layer is located on the gate dielectric layer. The insulating layer is located over the channel layer. The first source/drain electrode and the second source/drain electrode are located in the insulating layer, and connected to the channel layer. The second dielectric layer is beside one of the first source/drain electrode and the second source/drain electrode. The stop segment is embedded in the second dielectric layer.

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: This invention is related to a kind of teeth bleaching formulation containing the vegetative enzymes extracted from plant tubers with extensively applications in cosmetic dentistry. The enzymes are susceptible to promote the decomposition (dissociation) of peroxide compounds, thus the intermediate hydroxyl free radicals are generated to turn the unpleasant stained tooth into light or colorless appearance effectively. The composition of a whitening gel may comprising 2˜50 wt % of hydrogen peroxide, 0.003˜3 wt % vegetative enzyme extract, and transferring to alkalinity approximately pH 8˜13 to achieve the high efficiency dental bleaching usage.