Patents by Inventor Yen-Chun Lee
Yen-Chun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11978492Abstract: The disclosed system and method reduce on-chip power IR drop caused by large write current, to increase the write IO number or improve write throughput and to suppress write voltage ripple at the start and end of a write operation. The disclosed systems and methods are described in relation to stabilizing the bit line voltage for MRAMs, however, the disclosed systems and methods can be used to stabilize the bit line voltage of any memory configuration that draws large currents during short write pulses or, more generally, to selectively assist a power supply generator in supplying adequate power to a load at times of large power consumption.Type: GrantFiled: May 5, 2022Date of Patent: May 7, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-An Chang, Po-Hao Lee, Yi-Chun Shih
-
Patent number: 11948634Abstract: A memory device includes a plurality of memory elements. The memory device additionally includes a first current mirror that when in operation selectively outputs a first current to select a target memory cell as a first memory element of the plurality of memory elements. The memory device further includes a second current mirror that when in operation selectively outputs a second current to select the target memory cell as the first memory element of the plurality of memory elements.Type: GrantFiled: September 14, 2022Date of Patent: April 2, 2024Assignee: Micron Technology, Inc.Inventor: Yen Chun Lee
-
Publication number: 20240106104Abstract: An electronic device includes a device body and an antenna module disposed in the device body and including a conductive structure and a coaxial cable including a core wire, a shielding layer wrapping the core wire, and an outer jacket wrapping the shielding layer. The conductive structure includes a structure body and a slot formed on the structure body and penetrating the structure body in a thickness direction of the structure body. A section of the shielding layer extends from the outer jacket and is connected to the structure body. A physical portion of the structure body and the section of the shielding layer are respectively located on two opposite sides of the slot in a width direction of the slot. A section of the core wire extends from the section of the shielding layer and overlaps the slot and the physical portion in the thickness direction.Type: ApplicationFiled: September 8, 2023Publication date: March 28, 2024Applicant: COMPAL ELECTRONICS, INC.Inventors: Hung-Yu Yeh, Shih-Chia Liu, Yen-Hao Yu, Li-Chun Lee, Chih-Heng Lin, Jui-Hung Lai
-
Patent number: 11932714Abstract: A copolymer, a film composition and a composite material employing the same are provided. The copolymer is a copolymerization product of a composition, wherein the composition includes a monomer (a), a monomer (b) and a monomer (c). The monomer (a) is a compound having a structure represented by Formula (I), the monomer (b) is a compound having a structure represented by Formula (II), and the monomer (c) is a compound having a structure represented by Formula (III) wherein R1, R2, R3, R4, R5 and R6 are as defined in specification.Type: GrantFiled: July 22, 2022Date of Patent: March 19, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yen-Yi Chu, Yun-Ching Lee, Li-Chun Liang, Wei-Ta Yang, Hsiang-Chin Juan
-
Patent number: 11923886Abstract: An antenna device and a method for configuring the same are provided. The antenna device includes a grounding metal, a grounding part, a radiating part, a feeding part, a proximity sensor, and a sensing metal. The radiating part is electrically connected to the grounding metal through the grounding part. The feeding part is coupled to the grounding metal through a feeding point. The sensing metal is electrically connected to the proximity sensor. The sensing metal is separated from the radiating part at a distance. The distance is less than or equal to one thousandth of a wavelength corresponding to an operating frequency of the antenna device.Type: GrantFiled: August 27, 2021Date of Patent: March 5, 2024Assignee: COMPAL ELECTRONICS, INC.Inventors: Jhih-Ciang Chen, Shih-Chia Liu, Yen-Hao Yu, Li-Chun Lee, Yan-Ming Lin, Jui-Hung Lai
-
Patent number: 11894078Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.Type: GrantFiled: May 26, 2022Date of Patent: February 6, 2024Assignee: Micron Technology, Inc.Inventors: Karthik Sarpatwari, Xuan-Anh Tran, Jessica Chen, Jason A. Durand, Nevil N. Gajera, Yen Chun Lee
-
Patent number: 11862226Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a plurality of read voltages to the memory array based on the read request. The control circuit is further configured to perform a data analysis for a first set of data read based on the application of the plurality of read voltages and to derive a demarcation bias voltage (VDM) based on the data analysis. The control circuit is also configured to apply the VDM to the memory array to read a second set of data.Type: GrantFiled: August 31, 2021Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Karthik Sarpatwari, Fabio Pellizzer, Nevil N. Gajera, Yen Chun Lee, Ferdinando Bedeschi
-
Patent number: 11728005Abstract: Systems, methods and apparatus to implement bipolar read retry. In response to a determination that a first result of reading a set of memory cells using a first magnitude of read voltage is erroneous, a second magnitude of read voltage, greater than the first magnitude, is identified for the bipolar read retry. In the retry, a controller uses voltage drivers to apply, to the set of memory cells, first voltages of the second magnitude in a first polarity to obtain a second result of reading the set of memory cells and, after the second result is generated and in parallel with decoding the second result, apply second voltages of the second magnitude in a second polarity, opposite to the first polarity.Type: GrantFiled: September 6, 2022Date of Patent: August 15, 2023Assignee: Micron Technology, Inc.Inventors: Yen Chun Lee, Karthik Sarpatwari, Nevil N. Gajera
-
Patent number: 11664074Abstract: Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.Type: GrantFiled: June 2, 2021Date of Patent: May 30, 2023Assignee: Micron Technology, Inc.Inventors: Karthik Sarpatwari, Nevil N. Gajera, Lingming Yang, Yen Chun Lee, Jessica Chen, Francesco Douglas Verna-Ketel
-
Patent number: 11598058Abstract: The invention provides a warning sign device. The warning sign device comprises a sign body and a continuous track assembly. The continuous track assembly is disposed on the sign body.Type: GrantFiled: May 13, 2019Date of Patent: March 7, 2023Assignee: ASUSTEK COMPUTER INC.Inventors: Yen-Chun Lee, Hung-Ling Chen
-
Publication number: 20230067396Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a plurality of read voltages to the memory array based on the read request. The control circuit is further configured to perform a data analysis for a first set of data read based on the application of the plurality of read voltages and to derive a demarcation bias voltage (VDM) based on the data analysis. The control circuit is also configured to apply the VDM to the memory array to read a second set of data.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Karthik Sarpatwari, Fabio Pellizzer, Nevil N. Gajera, Yen Chun Lee, Ferdinando Bedeschi
-
Publication number: 20230018023Abstract: A memory device includes a plurality of memory elements. The memory device additionally includes a first current mirror that when in operation selectively outputs a first current to select a target memory cell as a first memory element of the plurality of memory elements. The memory device further includes a second current mirror that when in operation selectively outputs a second current to select the target memory cell as the first memory element of the plurality of memory elements.Type: ApplicationFiled: September 14, 2022Publication date: January 19, 2023Inventor: Yen Chun Lee
-
Publication number: 20220415429Abstract: Systems, methods and apparatus to implement bipolar read retry. In response to a determination that a first result of reading a set of memory cells using a first magnitude of read voltage is erroneous, a second magnitude of read voltage, greater than the first magnitude, is identified for the bipolar read retry. In the retry, a controller uses voltage drivers to apply, to the set of memory cells, first voltages of the second magnitude in a first polarity to obtain a second result of reading the set of memory cells and, after the second result is generated and in parallel with decoding the second result, apply second voltages of the second magnitude in a second polarity, opposite to the first polarity.Type: ApplicationFiled: September 6, 2022Publication date: December 29, 2022Inventors: Yen Chun Lee, Karthik Sarpatwari, Nevil N. Gajera
-
Publication number: 20220392535Abstract: Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.Type: ApplicationFiled: June 2, 2021Publication date: December 8, 2022Inventors: Karthik Sarpatwari, Nevil N. Gajera, Lingming Yang, Yen Chun Lee, Jessica Chen, Francesco Douglas Verna-Ketel
-
Patent number: 11475970Abstract: Systems, methods and apparatus to implement bipolar read retry. In response to a determination that a first result of reading a set of memory cells using a first magnitude of read voltage is erroneous, a second magnitude of read voltage, greater than the first magnitude, is identified for the bipolar read retry. In the retry, a controller uses voltage drivers to apply, to the set of memory cells, first voltages of the second magnitude in a first polarity to obtain a second result of reading the set of memory cells and, after the second result is generated and in parallel with decoding the second result, apply second voltages of the second magnitude in a second polarity, opposite to the first polarity.Type: GrantFiled: June 3, 2021Date of Patent: October 18, 2022Assignee: Micron Technology, Inc.Inventors: Yen Chun Lee, Karthik Sarpatwari, Nevil N. Gajera
-
Patent number: 11456032Abstract: A memory device includes a plurality of memory elements. The memory device additionally includes a first current mirror that when in operation selectively outputs a first current to select a target memory cell as a first memory element of the plurality of memory elements. The memory device further includes a second current mirror that when in operation selectively outputs a second current to select the target memory cell as the first memory element of the plurality of memory elements.Type: GrantFiled: January 29, 2021Date of Patent: September 27, 2022Assignee: Micron Technology, Inc.Inventor: Yen Chun Lee
-
Publication number: 20220284973Abstract: Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.Type: ApplicationFiled: May 26, 2022Publication date: September 8, 2022Inventors: Karthik Sarpatwari, Xuan-Anh Tran, Jessica Chen, Jason A. Durand, Nevil N. Gajera, Yen Chun Lee
-
Publication number: 20220284957Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.Type: ApplicationFiled: May 25, 2022Publication date: September 8, 2022Inventors: Yen Chun Lee, Nevil N. Gajera, Karthik Sarpatwari
-
Publication number: 20220246209Abstract: A memory device includes a plurality of memory elements. The memory device additionally includes a first current mirror that when in operation selectively outputs a first current to select a target memory cell as a first memory element of the plurality of memory elements. The memory device further includes a second current mirror that when in operation selectively outputs a second current to select the target memory cell as the first memory element of the plurality of memory elements.Type: ApplicationFiled: January 29, 2021Publication date: August 4, 2022Inventor: Yen Chun Lee
-
Patent number: 11367484Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.Type: GrantFiled: January 21, 2021Date of Patent: June 21, 2022Assignee: Micron Technology, Inc.Inventors: Yen Chun Lee, Nevil N. Gajera, Karthik Sarpatwari