Abstract: A security processing device for handling attacks including an attack detector, a programing time controller, a non-volatile memory device and a processing unit. The attack detector is used to detect whether an attack event occurs, and generate an attack trigger signal when the attack event occurs. The programing time controller is electrically connected to the attack detector, and used to update a first flag value when receiving the attack trigger signal. The non-volatile memory device is electrically connected to the program time controller, and used to store the first and the second flag values. The processing unit is electrically connected to the program time controller. When the security processing device is reset or boot-up, the programing time controller updates the second flag value and adjusts a time of a first instruction processed through the processing unit based on the first flag value and the second flag value.

Abstract: The invention provides a method for improving sarcopenia of a subject in need thereof by using Phellinus linteus, in which the method includes administering an effective dose of composition to the subject, and the composition includes Phellinus linteus (NITE BP-03321 and BCRC 930210) as an effective substance. By using the aforementioned composition including an extract of a fermented product of the Phellinus linteus and/or its derivative, diameters of myotubes, amounts of muscles and muscle muscular endurance can be maintained, thereby improving sarcopenia.

Abstract: A method of reversing aquifer parameter with skin effect is used for reversing an aquifer parameter of a monitoring well and a surrounding area thereof. The method includes steps of: performing a slug test on the monitoring well, and measuring a first water level change of the monitoring well by a water level meter; setting a parameter assembly having a plurality of hypothetical aquifer parameters; converting the hypothetical aquifer parameters through a programming language, and then respectively calculating a plurality of second water level changes; respectively calculating a plurality of function values through an objective function according to the first water level change and the second water level changes, and selecting one hypothetical aquifer parameter corresponding to one function value that meets a convergence condition from the function values; taking the hypothetical aquifer parameter that meets the convergence condition as the aquifer parameter.

Abstract: A method for forming a semiconductor device structure includes forming first nanostructures and second nanostructures over a substrate. The method also includes forming a first metal gate layer surrounding the first nanostructures and over the first nanostructures and the second nanostructures. The method also includes etching back the first metal gate layer over the first nanostructures and the second nanostructures. The method also includes removing the first metal gate layer over the second nanostructures. The method also includes forming a second metal gate layer surrounding the second nanostructures and over the first nanostructures and the second nanostructures.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.

Abstract: A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.

Abstract: The invention relates to Proprotein Convertase Subtilisin Kexin type 9 (PCSK9) antagonists, such as antibodies and fragments, as well as methods, uses and combinations.

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A semiconductor chip is bonded on a carrier, wherein the semiconductor chip comprises a plurality of conductive pads. An insulating material layer is formed over the carrier and encapsulating the semiconductor chip, wherein a thickness of the insulating material layer is greater than a thickness of the semiconductor chip. A first surface of the insulating material layer is patterned to form first openings that expose the conductive pads of the semiconductor chip, and second openings that penetrate through the insulating material layer. A plurality of conductive posts is formed in the first openings, wherein the plurality of conductive posts is electrically connected to the plurality of conductive pads of the semiconductor chip. A plurality of conductive vias is formed in the second opening.

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A semiconductor chip is bonded on a carrier, wherein the semiconductor chip comprises a plurality of conductive pads. An insulating material layer is formed over the carrier and encapsulating the semiconductor chip, wherein a thickness of the insulating material layer is greater than a thickness of the semiconductor chip. A first surface of the insulating material layer is patterned to form first openings that expose the conductive pads of the semiconductor chip, and second openings that penetrate through the insulating material layer. A plurality of conductive posts is formed in the first openings, wherein the plurality of conductive posts is electrically connected to the plurality of conductive pads of the semiconductor chip. A plurality of conductive vias is formed in the second opening.

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Abstract: Primarily disclosed is a wafer-level chip-scale-package (WLCSP) for wire-bonding connection. A first encapsulating layer is formed over a passivation layer of a chip. An RDL (redistribution wiring layer) is formed on the first encapsulating layer. A plurality of wire-bonding pads are stacked on the wiring terminals of the RDL on the first encapsulating layer. Each wire-bonding pad has a top surface and a sidewall. A surface plated layer completely covers the top surfaces of the wire-bonding pads. A second encapsulating layer is formed over the first encapsulating layer to encapsulate the RDL and the sidewalls of the wire-bonding pads. The openings of the second encapsulating layer are smaller than the top surfaces of the corresponding wire-bonding pads to partially encapsulate the surface plated layer. Accordingly, it can resolve the issue of die crack when wire-bonding on thinned chips.

Abstract: A fabricating method of a color filter substrate includes following steps. First, a base is provided. A patterned color filter film layer having a plurality of recesses is then formed on the base. Next, a common electrode layer is formed on the patterned color filter film layer and the base. Here, the common electrode layer conforms to surfaces of the recesses. Thereafter, a plurality of shelters are formed on the common electrode layer and correspond to the recesses.

Abstract: A color filter substrate including a base, a patterned color filter film layer, a common electrode layer and shelters is provided. The patterned color filter film layer is disposed on the base. Here, the patterned color filter film layer has recesses. Additionally, the patterned color filter film layer and the base are covered by the common electrode layer conforming to surfaces of the recesses. Moreover, the recesses and the common electrode layer are covered by the shelters.

Abstract: A packaging substrate includes: a core board having opposite first and second surfaces and a cavity penetrating therethrough; a semiconductor chip disposed in the cavity and having an active surface with electrode pads and an opposite inactive surface; a first reinforcing dielectric layer containing a reinforcing material disposed on the first surface and the active surface and filling the gap between the chip and the cavity; a second reinforcing dielectric layer containing a reinforcing material disposed on the second surface and the inactive surface and filling the gap between the chip and the cavity; and first and second wiring layers disposed on the first and second reinforcing dielectric layers respectively and the first wiring layer electrically connecting to the electrode pads. The first and second reinforcing dielectric layers enhance the support force of the entire structure to thereby prevent delamination of the wiring layers from the dielectric layers and increase product yield and reliability.