Abstract: Methods and apparatus of for video coding using sub-block based affine mode are disclosed. In one method, if affine fallback is used or the control-point motion vectors are the same, the sub-block based affine mode is disabled in order to reduce computational complexity. According to another method for video coding using a coding tool belonging to a coding tool group comprising Prediction Refinement with Optical Flow (PROF) and Bi-Directional Optical Flow (BDOF), predictor refinement is derived for pixels of a target subblock of the current block, where a step to derive the predictor refinement comprises to derive gradients for the pixels of the target subblock of the current block and to right-shift the first gradients by a common shift.

Abstract: A wearable device includes a conducting frame, a circuit board, and a grounding member. The conducting frame includes a first part and a second part that are separated. The circuit board has a system grounding surface and is disposed inside the conducting frame. The grounding member is disposed inside the conducting frame and connected to the first part. The first part and the grounding member are formed as a first antenna. The first part has a first feeding terminal. The grounding member has a first grounding terminal, and the first grounding terminal is connected to the system grounding surface of the circuit board. The second part is formed as a second antenna. The second antenna has a second feeding terminal, a second grounding terminal, and a third grounding terminal. The second and the third grounding terminals are connected to the system grounding surface of the circuit board.

Abstract: Encoding methods and apparatuses include receiving input video data of a current block in a current picture and applying a Cross-Component Adaptive Loop Filter (CCALF) processing on the current block based on cross-component filter coefficients to refine chroma components of the current block according to luma sample values. The method further includes signaling two Adaptive Loop Filter (ALF) signal flags and two CCALF signal flags in an Adaptation Parameter Set (APS) with an APS parameter type equal to ALF or parsing two ALF signal flags and two CCALF signal flags from an APS with an APS parameter type equal to ALF, signaling or parsing one or more Picture Header (PH) CCALF syntax elements or Slice Header (SH) CCALF syntax elements, wherein both ALF and CCALF signaling are present either in a PH or SH, and encoding or decoding the current block in the current picture.

Abstract: The disclosure provides a method of active immunotherapy for a cancer patient, comprising administering vaccines against Globo series antigens (i.e., Globo H, SSEA-3 and SSEA-4). Specifically, the method comprises administering Globo H-CRM197 (OBI-833/821) in patients with cancer. The disclosure also provides a method of selecting a cancer patient who is suitable as treatment candidate for immunotherapy. Exemplary immune response can be characterized by reduction of the severity of disease, including but not limited to, prevention of disease, delay in onset of disease, decreased severity of symptoms, decreased morbidity and delayed mortality.

Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Abstract: Video processing methods and apparatuses for coding a current block comprise receiving input data of a current block, partitioning the current block into multiple sub-blocks, deriving sub-block MVs for the current block according to a sub-block motion compensation coding tool, constraining the sub-block MVs to form constrained sub-block MVs, and encoding or decoding the current block using the constrained sub-block MVs, and applying motion compensation to the current block using the constrained sub-block MVs to encode or decode the current block. The sub-block MVs may be constrained according to a size, width, or height of the current block or a sub-block, an inter prediction direction of one of control point MVs of the current block, the current block, or current sub-block, the control point MVs, or a combination of the above.

Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: The present disclosure provides a method for fabricating a nickel-cerium dioxide-aluminum oxide hybrid nanoparticle cluster catalyst. The method includes a solution preparation step, an aerosolizing step, a drying step, a first calcining step, a reducing gas adding step, and a second calcining step. The solution preparation step is provided for preparing a precursor solution. The aerosolizing step is performed for obtaining an atomized droplet. The drying step is performed for converting to a precursor crystallite. The first calcining step is performed for obtaining an oxidation state catalyst. The reducing gas adding step is performed for adding hydrogen. The second calcining step is performed for obtaining the nickel-cerium dioxide-aluminum oxide hybrid nanoparticle cluster catalyst.

Abstract: Provided is an anesthetic composition for locally administering a local anesthetic agent to a subject in need thereof. The anesthetic composition has a lipid based complex prepared by hydrating a lipid cake containing a local anesthetic agent and a lipid mixture with an aqueous buffer solution at a pH higher than 5.5. Also provided is a method to prepare an anesthetic composition using a simpler and more robust for large-scale manufacture and for providing a high molar ratio of local anesthetic agent to phospholipid content as compared to the prior art. This anesthetic composition has a prolonged duration of efficacy adapted to drug delivery.

Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.

Abstract: A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.

Abstract: A monitoring system and a monitoring method of network latency are provided. The monitoring method includes: making a server communicatively connect to a first host and a second host, wherein the first host provides a first virtual machine operating a first application and the second host provides a second virtual machine operating a second application; and calculating, by the server, time latency information associated with a communication between the first application and the second application according to data obtained from the first host and the second host, and displaying the time latency information through a visual interface, wherein the time latency information includes a total latency of the communication between the first application and the second application.

Abstract: Methods and apparatus for video coding are disclosed. According to one method, First ALF (Adaptive Loop Filter) processing is applied to the reconstructed chroma samples for a target reconstructed chroma sample to generate a first filtered chroma sample. Second ALF processing is applied to the related reconstructed luma samples to generate a second filtered chroma sample for the target reconstructed chroma sample, where positions of the related reconstructed luma samples selected for the second ALF processing are determined according to the target chroma format. According to another method, the luma ALF and the cross-component ALF have the same filter coefficient precision.

Abstract: To provide a gas-liquid separator of a water electrolysis system, comprising: a liquid feeding atomizer and a gas-liquid separation chamber, wherein the liquid feeding atomizer includes a liquid feeding pressurized tube; and an atomizing spray head, in which the atomizing spray head converts a gas-liquid mixed liquor after pressurized by the liquid feeding pressurized tube into a mist droplet gas-liquid mixture. The gas-liquid separation chamber comprises a spiral flowing way, and the spiral flowing way extends the time that the mist droplet gas-liquid mixture spraying into the gas-liquid separation chamber flows downwards to the bottom of the gas-liquid separation chamber; an ultrasonic oscillation mechanism; a stirrer; an internal reservoir; and a filter mechanism, which performs the gas-liquid separation for unbroken bubbles in the mist droplet gas-liquid mixture through the pore difference.

Abstract: The present disclosure provides a semiconductor device and a method for forming a semiconductor device. The semiconductor device includes a substrate, and a first gate dielectric stack over the substrate, wherein the first gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, wherein the first ferroelectric layer includes a first portion made of a ferroelectric material in orthorhombic phase, a second portion made of the ferroelectric material in monoclinic phase, and a third portion made of the ferroelectric material in tetragonal phase, wherein a total volume of the second portion is greater than a total volume of the first portion, and the total volume of the first portion is greater than a total volume of the third portion.

Abstract: A video system that applies constraints on block partitioning is provided. The system receives a partitioning control parameter from a bitstream specifying a maximum block size for enabling ternary-tree split that is constrained to be 64 or smaller. The system receives data from a bitstream for a block of pixels to be decoded as a current block of a current picture of a video. The system splits the current block into one or more partitions recursively, wherein ternary split is disallowed for a partition of the current block unless the partition is less than or equal to the maximum block size. The system reconstructs the one or more partitions of the current block.

Abstract: A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The substrate has first and second board surfaces opposite to each other. The vias penetrate through the first board surface and the second board surface, and a part of the vias is disposed in a first die-bonding region on which a chip is to be arranged. The electrodes extend from the first board surface to the second board surface through the vias. The dam is formed on the first board surface to surround the first die-bonding region, and the dam has a height higher than that of the chip. The metal shielding layer covers the dam and a part of the first board surface that do not overlap with the electrodes.

Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.