Abstract: A bone substitute composition includes a bone substitute matrix and a conditioning solution. The bone substitute matrix includes 85% to 98% by weight of alkaline calcium phosphate powder, 1% to 10% by weight of a polymer, and 1% to 5% by weight of a crosslinker. The conditioning solution includes 90% to 97% by weight of water, 1% to 5% by weight of a phosphate, and 1% to 5% by weight of a water-soluble acidic compound.

Abstract: The invention provides a broadband bipolar mmWave antenna comprising: a first substrate having an upper surface and a bottom surface; a second substrate attached to the bottom surface of the first substrate; a parasitic element disposed in between the first and second substrates; a patch formed on the upper surface of the first substrate; a first feeding line coupled with the patch and formed on the upper surface of the first substrate; a second feeding line coupled with the patch and formed on the upper surface of the first substrate; and a via formed passing through the first substrate, the parasitic element and the second substrate.

Abstract: A signal transmitting element is used to solve the problem that an additional surgery is required to remove the conventional vascular monitoring element after completing the detecting task. The signal transmitting element comprises a body made of a specific biodegradable material. The body includes a signal sensing portion including a structure configured to sense a blood flow information of a blood vessel surrounded and contacted by the body, thereby generating a blood vessel signal; and a signal transmitting portion coupled with the signal sensing portion for receiving the blood vessel signal and including a specific structure configured to convert the blood vessel signal into a transmission signal.

Abstract: An electronic device with a display module includes a device body and a display module. The display module is connected to the device body. The display module includes a housing, a protective layer, a transparent substrate, a plurality of visible-light light-emitting diodes, and an ultraviolet light assembly. The protective layer is disposed on the housing. An accommodating space is disposed between the housing and the protective layer. The transparent substrate has a first surface and a second surface opposite to each other. The visible-light light-emitting diodes are two-dimensionally disposed on the first surface. The ultraviolet light assembly is disposed on the second surface. The transparent substrate, the visible-light light-emitting diodes, and the ultraviolet light assembly are disposed in the accommodating space, and the ultraviolet light assembly emits an ultraviolet light toward the protective layer selectively.

Abstract: A keyswitch structure includes a base plate, a keycap, and a support mechanism. The support mechanism supports the keycap above the base plate. An outer support of the support mechanism includes a reinforcing body and a connecting structure fixed on the reinforcing body. The outer support is connected to the base plate and the keycap through the connecting structure. In an embodiment, the reinforcing body has two openings. Two inner supports of the support mechanism are pivotally connected to the connecting structure and are located in the two openings, respectively. In another embodiment, the reinforcing body as a whole extends along a plane. The reinforcing body has a bent fringe, which is inserted into the connecting structure and is not perpendicular to the plane.

Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.

Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.

Abstract: In some embodiments, a method is provided. The method includes identifying an incident situation based upon a sensor detecting an abnormal condition. One or more life safety systems are queried to obtain life safety system data. One or more databases, comprising equipment information, chemical information, personnel information, and/or emergency response contingency procedures, are queried to obtain on-site information. The life safety system data and the on-site information are integrated together to generate incident situation information. The incident situation information is displayed through an electronic display.

Abstract: A semiconductor device includes a substrate, an interfacial layer formed on the semiconductor substrate, and a high-k dielectric layer formed on the interfacial layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity. A first concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the p-type transistor is different from a second concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the n-type transistor.

Abstract: A memory device for CIM has a memory array including a plurality of memory cells arranged in an array of rows and columns. The memory cells have a first group of memory cells and a second group of memory cells. Each row of the array has a corresponding word line, with each memory cell of a row of the array coupled to the corresponding word line. Each column of the array has a corresponding bit line, with each memory cell of a column of the array coupled to the corresponding bit line. A control circuit is configured to select the first group of memory cells or the second group of memory cells in response to a group enable signal.

Abstract: An electronic device includes a sustaining layer, multiple substrates, multiple photoelectric units, and multiple signal layers. The substrates are arranged on a contact surface of the sustaining layer. A first end edge of at least one substrate approaches a first end edge of the sustaining layer, and a first side edge of one substrate is adjacent to a second side edge of another substrate. The photoelectric units are arranged on the first or/and second surfaces of the substrates. The signal layers are arranged on the substrates and electrically connected to the photoelectric units.

Abstract: A semiconductor package device is provided. The semiconductor package device includes a chip and a redistribution layer disposed on the chip and electrically connected to the chip. The redistribution layer includes a plurality of first metal lines and a plurality of second metal lines, wherein at least one of the second metal lines is disposed between two adjacent first metal lines. The included angle between the at least one of the second metal lines and the two adjacent first metal lines is greater than or equal to 0 degrees and less than or equal to 10 degrees. The first width of one of the two adjacent first metal lines is greater than the second width of the at least one of the second metal lines.

Abstract: One or more computing devices, systems, and/or methods are provided. In an example, a first performance metric score may be determined based upon first content item text. A plurality of similarity scores associated with a plurality of sets of content item text may be determined. One or more sets of content item text may be selected from among the plurality of sets of content item text based upon the plurality of similarity scores and a plurality of performance metric scores associated with the plurality of sets of content item text. The plurality of performance metric scores may comprise one or more performance metric scores associated with the one or more sets of content item text. The one or more performance metric scores may be higher than the first performance metric score. One or more representations of the one or more sets of content item text may be displayed.

Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Abstract: A method includes receiving an integrated circuit (IC) design layout including a layout block, where the layout block including first line patterns disposed along a first direction, extending lengths of the first line patterns, connecting portions of the first line patterns disposed within a distance less than a preset value, forming second line patterns disposed outside the layout block parallel to the first line patterns, forming mandrel bar patterns overlapping edges of the layout block, where the mandrel bar patterns oriented along a second direction perpendicular to the first direction, and outputting a pattern layout for mask fabricating, where the pattern layout includes the layout block, the first and second line patterns, and the mandrel bar patterns.

Abstract: A method of manufacturing a semiconductor device includes: forming mutually parallel three-dimensional (3D) conductive channels coated with a conformal sacrificial layer, the 3D conductive channels coated with the conformal sacrificial layer being formed on a semiconductor substrate; depositing a dielectric material to fill spaces between the 3D conductive channels coated with the conformal sacrificial layer, wherein a portion or all of the deposited dielectric material is doped with boron, lithium, or beryllium; performing chemical mechanical polishing (CMP) to remove a top portion of the deposited dielectric material and to expose tops of the 3D conductive channels; and after the CMP, removing the conformal sacrificial layer coating the 3D conductive channels by etching to form 3D dielectric features spaced apart from the 3D conductive channels and comprising the deposited dielectric material.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.

Abstract: An electronic device includes two bodies, at least one hinge structure, a functional assembly, and at least one linkage structure. The two bodies are pivotally connected to each other through the hinge structure. The functional assembly is movably disposed on one of the two bodies. The linkage structure is connected between the two bodies, and the functional assembly is connected to the linkage structure. The linkage structure is adapted to drive the functional assembly to move relative to the corresponding body as the two bodies are rotated relative to each other.