Patents by Inventor Yen-Lin Huang
Yen-Lin Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178319Abstract: A semiconductor device includes a substrate, an interfacial layer formed on the semiconductor substrate, and a high-k dielectric layer formed on the interfacial layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity. A first concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the p-type transistor is different from a second concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the n-type transistor.Type: ApplicationFiled: February 2, 2024Publication date: May 30, 2024Inventors: Hsiang-Pi Chang, Yen-Tien Tung, Dawei Heh, Chung-Liang Cheng, I-Ming Chang, Yao-Sheng Huang, Tzer-Min Shen, Huang-Lin Chao
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Publication number: 20240164111Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.Type: ApplicationFiled: January 23, 2024Publication date: May 16, 2024Inventors: Song-Fu Liao, Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Integration scheme for breakdown voltage enhancement of a piezoelectric metal-insulator-metal device
Patent number: 11984261Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.Type: GrantFiled: August 25, 2021Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao -
Patent number: 11968844Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.Type: GrantFiled: November 6, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Min Lee, Ming-Yuan Song, Yen-Lin Huang, Shy-Jay Lin, Tung-Ying Lee, Xinyu Bao
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Patent number: 11920778Abstract: A ventilation fan includes a housing having an opening, a grille structure positioned to cover the opening, a fan module provided in the housing and a function module. The grille structure includes a base defining an outlet, and a grille support spaced apart from the base and connected by the connecting columns A radial inlet is formed between the base and the grille support is in communication with the outlet. The base includes a holder having a holding opening axially downward and faced away from the housing. The function module is disposed within the holder through the holding opening.Type: GrantFiled: September 30, 2022Date of Patent: March 5, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Yu-Hsiang Huang, Yen-Lin Chen, Chih-Hua Lin
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Patent number: 11917144Abstract: Various schemes for realizing efficient in-loop filtering are described, manifested in low latency and reduced hardware cost for an in-loop filter comprising at least two filtering stages. An apparatus receives pixel data of a current block of a picture and one or more neighboring blocks thereof, based on which the apparatus performs a filtering operation and generates a filtered block that includes completely filtered sub-blocks and partially filtered sub-blocks. The apparatus further outputs an output block that includes the completely filtered sub-blocks as well as a respective portion of each of the partially filtered sub-blocks, wherein the respective portion is adjacent to one of the completely filtered sub-blocks.Type: GrantFiled: June 19, 2022Date of Patent: February 27, 2024Assignee: MediaTek Inc.Inventors: Yueh-Lin Wu, Min-Hao Chiu, Yen-Chieh Huang
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Patent number: 11917831Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.Type: GrantFiled: August 5, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Song-Fu Liao, Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
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Publication number: 20230389439Abstract: A memory device includes a substrate, a spin-orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) film stack, a connecting via and a shielding structure. The SOT layer is disposed on the substrate. The MTJ film stack is formed over SOT layer and on the substrate. The connecting via is disposed on and electrically connected to the MTJ film stack. The shielding structure is laterally surrounding the MTJ film stack and disposed on the SOT layer, wherein the shielding structure includes a first dielectric layer, a high magnetic permeability layer and a second dielectric layer, the first dielectric layer is in contact with the SOT layer and the MTJ film stack, and the high magnetic permeability layer is sandwiched between the first dielectric layer and the second dielectric layer.Type: ApplicationFiled: May 30, 2022Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Lin Huang, Ming-Yuan Song, Chien-Min Lee, Nuo Xu, Shy-Jay Lin
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Publication number: 20230363290Abstract: A memory device is provided. The memory device includes a substrate, a spin-orbit torque layer and a magnetic tunneling junction (MTJ). The MTJ stacks with the spin-orbit torque layer over the substrate and includes a synthetic free layer, a barrier layer and a reference layer. The synthetic free layer includes a synthetic antiferromagnetic structure, a first spacer layer and a free layer, wherein the synthetic antiferromagnetic structure is disposed between the spin-orbit torque layer and the free layer. The barrier layer is disposed beside the synthetic free layer. The reference layer is disposed beside the barrier layer.Type: ApplicationFiled: July 19, 2023Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Lin Huang, Ming-Yuan Song, Chien-Min Lee, Shy-Jay Lin
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Publication number: 20230354719Abstract: A memory device including a pair of magnetic conductive posts, a Spin-Hall-Effect-assisted (SHE-assisted) layer, and a magnetic tunneling junction (MTJ) structure. The Spin-Hall-Effect-assisted (SHE-assisted) layer is disposed over and electrically connected to the pair of magnetic conductive posts. The magnetic tunneling junction (MTJ) structure has in-plane magnetic anisotropy, wherein the MTJ structure is disposed on the SHE-assisted layer, and the pair of magnetic conductive posts provide an in-plane magnetic field during a write operation of the MTJ structure.Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shy-Jay Lin, Nuo Xu, Yen-Lin Huang
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Publication number: 20230345738Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.Type: ApplicationFiled: June 15, 2023Publication date: October 26, 2023Inventors: Shy-Jay Lin, Chien-Min Lee, Hiroki Noguchi, MingYuan Song, Yen-Lin Huang, William Joseph Gallagher
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Patent number: 11766847Abstract: A multilayer plate with composite material and a method thereof are described. The multilayer plate includes an aluminum-based thin sheet and a composite material layer. The aluminum-based thin sheet includes a first passivation layer, an aluminum-based metal layer, and a second passivation layer sequentially. The aluminum-based thin sheet includes a first surface and a second surface opposite to the first surface. The first and second surfaces are set with micro holes. A diameter of the micro holes in the second surface is ranging from 0.5 ?m to 10 ?m. The composite material layer includes a thermoplastic polymer and a fiber material. The composite material layer has a third surface and a fourth surface opposite each other. The second surface is adjacent to or connected to the third surface. At least one portion of the thermoplastic polymer fills into the micro holes in the second surface.Type: GrantFiled: April 8, 2021Date of Patent: September 26, 2023Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTREInventors: Yen-Lin Huang, Pei-Jung Tsai, Chi-Wah Keong
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Patent number: 11765984Abstract: A memory device is provided. The memory device includes a substrate, a spin-orbit torque layer and a magnetic tunneling junction (MTJ). The MTJ stacks with the spin-orbit torque layer over the substrate and includes a synthetic free layer, a barrier layer and a reference layer. The synthetic free layer includes a synthetic antiferromagnetic structure, a first spacer layer and a free layer, wherein the synthetic antiferromagnetic structure is disposed between the spin-orbit torque layer and the free layer. The barrier layer is disposed beside the synthetic free layer. The reference layer is disposed beside the barrier layer.Type: GrantFiled: June 22, 2021Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Lin Huang, Ming-Yuan Song, Chien-Min Lee, Shy-Jay Lin
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Publication number: 20230292631Abstract: Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.Type: ApplicationFiled: April 28, 2023Publication date: September 14, 2023Inventors: Chien-Min Lee, Shy-Jay Lin, Yen-Lin Huang, MingYuan Song, Tung Ying Lee
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Patent number: 11723218Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.Type: GrantFiled: March 29, 2021Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shy-Jay Lin, Chien-Min Lee, Hiroki Noguchi, Mingyuan Song, Yen-Lin Huang, William Joseph Gallagher
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Patent number: 11706999Abstract: Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.Type: GrantFiled: July 7, 2021Date of Patent: July 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Min Lee, Shy-Jay Lin, Yen-Lin Huang, MingYuan Song, Tung Ying Lee
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Patent number: 11672186Abstract: Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.Type: GrantFiled: July 7, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Min Lee, Shy-Jay Lin, Yen-Lin Huang, MingYuan Song, Tung Ying Lee
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Publication number: 20230071950Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.Type: ApplicationFiled: November 6, 2022Publication date: March 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Min Lee, Ming-Yuan Song, Yen-Lin Huang, Shy-Jay Lin, Tung-Ying Lee, Xinyu BAO
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Patent number: 11538858Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.Type: GrantFiled: June 29, 2021Date of Patent: December 27, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Min Lee, Ming-Yuan Song, Yen-Lin Huang, Shy-Jay Lin, Tung-Ying Lee, Xinyu Bao
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Publication number: 20220285609Abstract: A memory device is provided. The memory device includes a substrate, a spin-orbit torque layer and a magnetic tunneling junction (MTJ). The MTJ stacks with the spin-orbit torque layer over the substrate and includes a synthetic free layer, a barrier layer and a reference layer. The synthetic free layer includes a synthetic antiferromagnetic structure, a first spacer layer and a free layer, wherein the synthetic antiferromagnetic structure is disposed between the spin-orbit torque layer and the free layer. The barrier layer is disposed beside the synthetic free layer. The reference layer is disposed beside the barrier layer.Type: ApplicationFiled: June 22, 2021Publication date: September 8, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Lin Huang, Ming-Yuan Song, Chien-Min Lee, Shy-Jay Lin