Patents by Inventor Yen-Lin Liu

Yen-Lin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984489
    Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiu Liu, Feng-Cheng Yang, Tsung-Lin Lee, Wei-Yang Lee, Yen-Ming Chen, Yen-Ting Chen
  • Patent number: 11966241
    Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng Chen, Yen-Lin Liu, Chia-Wei Hsu, Jo-Yu Wu, Chang-Fen Hu, Shao-Yu Li, Bo-Ting Chen
  • Publication number: 20230009027
    Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
    Type: Application
    Filed: February 11, 2022
    Publication date: January 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng Chen, Yen-Lin LIU, Chia-Wei Hsu, Jo-Yu Wu, CHANG-FEN HU, Shao-Yu Li, Bo-Ting Chen
  • Patent number: 11081363
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
  • Publication number: 20200118834
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Application
    Filed: December 13, 2019
    Publication date: April 16, 2020
    Inventors: Sheng-Fang CHENG, Chen - Chih WU, Chien-Yuan LEE, Yen-Lin LIU
  • Patent number: 10510554
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
  • Publication number: 20190109014
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 11, 2019
    Inventors: Sheng-Fang CHENG, Chen - Chih WU, Chien-Yuan LEE, Yen-Lin LIU
  • Patent number: 10170333
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
  • Publication number: 20180233377
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 16, 2018
    Inventors: Sheng-Fang CHENG, Chen - Chih WU, Chien-Yuan LEE, Yen-Lin LIU
  • Patent number: 9941141
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
  • Publication number: 20170194165
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Application
    Filed: March 20, 2017
    Publication date: July 6, 2017
    Inventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
  • Patent number: 9601625
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Fang Cheng, Yen-Lin Liu, Chen-Chih Wu, Chien-Yuan Lee
  • Patent number: 9425616
    Abstract: An RC triggered ESD protection device comprises a discharge transistor, a driver circuit and a trigger circuit. The trigger circuit comprises a plurality of native NMOS transistors connected in parallel with a plurality of PMOS transistors operating as resistors. The relatively small resistance of the plurality of native NMOS transistors helps to keep a stable RC time constant value so that the ESD protection device can avoid a leakage current during a power up operation.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Lin Liu, Kuo-Ji Chen, Tzu-Yi Yang
  • Publication number: 20150021713
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Application
    Filed: July 14, 2014
    Publication date: January 22, 2015
    Inventors: Sheng-Fang Cheng, Yen-Lin Liu, Chen-Chih Wu, Chien-Yuan Lee
  • Publication number: 20130016445
    Abstract: An RC triggered ESD protection device comprises a discharge transistor, a driver circuit and a trigger circuit. The trigger circuit comprises a plurality of native NMOS transistors connected in parallel with a plurality of PMOS transistors operating as resistors. The relatively small resistance of the plurality of native NMOS transistors helps to keep a stable RC time constant value so that the ESD protection device can avoid a leakage current during a power up operation.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 17, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Lin Liu, Kuo-Ji Chen, Tzu-Yi Yang
  • Publication number: 20040200161
    Abstract: The prefab external-wall structure is provided to increase the resisting strength of the external-wall against the external destruction force under the condition that the original wall strength is not damaged. The external-wall structure mainly comprises a main frame, a honeycomb structural board and an outer decorative wall-portion, wherein the main frame has on the two ends thereof a first receiving recess and a second receiving recess for embedding respectively therein the honeycomb structural board and the outer decorative wall-portion, and they are firmly stuck with silicone adhesive material. The main frame between the first and the second receiving recesses is formed therearound cut grooves for the purpose of fixing the external-wall structure of the present invention onto the wall of a building using fixing members.
    Type: Application
    Filed: April 8, 2003
    Publication date: October 14, 2004
    Inventor: Yen-Lin Liu