Abstract: A clock and data recovery device and a jitter tolerance enhancement method thereof are provided. The clock and data recovery device includes a clock and data recovery circuit and a jitter tolerance enhancement circuit. A data input terminal of the clock and data recovery circuit is suitable for receiving a data signal. The clock and data recovery circuit recovers the data signal to a clock. The jitter tolerance enhancement circuit is coupled to the data input terminal of the clock and data recovery circuit to receive the data signal. The jitter tolerance enhancement circuit detects a correlation between the data signal and the clock and correspondingly adjusts a loop gain of the clock and data recovery circuit according to the correlation.

Abstract: A clock and data recovery (CDR) circuit is provided. A phase detection circuit receives an input signal and a clock signal to output a first voltage signal. A first comparing circuit determines whether the first voltage signal is within a voltage range to output a first up signal and a first down signal. A counting circuit updates a counting value according to the input signal and the clock signal. A second comparing circuit determines whether the counting value is within a value range to output a second up signal and a second down signal. A selection circuit outputs a second voltage signal according to the first up signal, the first down signal, the second up signal, and the second down signal. A voltage controlled oscillator outputs the clock signal according to the first voltage signal and the second voltage signal.

Abstract: A clock and data recovery circuit and a method for estimating jitter tolerance thereof are provided. A first phase signal is generated by a phase detector, and a second phase signal is used to generate a clock signal. The second phase signal is set to be identical to the first phase signal during an operation mode. A counting is started and the first phase signal is inversed to generate the second phase signal during a test mode. Whether a data signal has an error is determined. The counting is stopped to generate a count value when determining that the data signal has the error during the test mode. A tracing speed is computed according to the count value and a predetermined unit interval.

Abstract: A half-rate clock and data recovery (CDR) circuit includes a first and a second gated voltage-controlled oscillators (GVCOs) and a first and a second frequency detectors. The first frequency detector generates a first output current according to a reference signal and a second divided clock, and the second frequency detector generates a second output current according to a first divided clock and the second divided clock. A loop filter converts either the first output current or the second output current to a first control voltage to control the second clock, and generates a second control voltage according to the first control voltage to control the first clock. A lock detector receives the reference signal and the second divided clock, and accordingly generates a lock signal.

Abstract: A half-rate clock and data recovery (CDR) circuit includes a first and a second gated voltage-controlled oscillators (GVCOs) and a first and a second frequency detectors. The first frequency detector generates a first output current according to a reference signal and a second divided clock, and the second frequency detector generates a second output current according to a first divided clock and the second divided clock. A loop filter converts either the first output current or the second output current to a first control voltage to control the second clock, and generates a second control voltage according to the first control voltage to control the first clock. A lock detector receives the reference signal and the second divided clock, and accordingly generates a lock signal.

Abstract: An adaptive switched-capacitor equalizer includes a first variable capacitor that is switchably connected between an input voltage and an output voltage, and a second variable capacitor that is switchably connected between the input voltage and the output voltage. The equalizer operates in a sequence of three phases, in a first phase of which the first variable is reset; in a second phase of which the first variable capacitor and the second variable capacitor are electrically connected in parallel between the input voltage and the output voltage; in a third phase of which calibration is performed according to the input voltages received in sequence.

Abstract: A clock and data recovery (CDR) architecture which includes a frequency detector, a phase detector, a phase charge pump circuit, a frequency charge pump circuit and a voltage controlled oscillator is provided. The phase detector is configured to only include four AND gates to receive and evaluate the intermediate signals, generated by the frequency detector, and accordingly generate a phase control signal. The voltage controlled oscillator is configured to output a plurality of clock signals with different phases according to the current signals outputted from the phase and frequency charge pump circuits, and select at least one of the plurality of clock signals with different phases for sampling a data signal.

Abstract: A clock and data recovery (CDR) architecture which includes a frequency detector, a phase detector, a phase charge pump circuit, a frequency charge pump circuit and a voltage controlled oscillator is provided. The phase detector is configured to only include four AND gates to receive and evaluate the intermediate signals, generated by the frequency detector, and accordingly generate a phase control signal. The voltage controlled oscillator is configured to output a plurality of clock signals with different phases according to the current signals outputted from the phase and frequency charge pump circuits, and select at least one of the plurality of clock signals with different phases for sampling a data signal.