Patents by Inventor Yen-Po Lin

Yen-Po Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240165170
    Abstract: The present invention provides a method for preventing and/or treating a NSAID-induced gastric ulcer. The method comprises administrating an effective amount of a lactic acid bacterium set to a subject. The lactic acid bacterium set comprises Lactobacillus plantarum GKD7 and Pediococcus acidilactici GKA4.
    Type: Application
    Filed: March 6, 2023
    Publication date: May 23, 2024
    Applicant: GRAPE KING BIO LTD.
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shin-Wei LIN, You-Shan TSAI, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, Zi-He WU, Yen-Po CHEN, Tzu Chun LIN
  • Patent number: 11984580
    Abstract: Provided is an anode particulate for a lithium battery, the particulate comprising a polymer foam material having pores and a single or a plurality of primary particles of an anode active material embedded in or in contact with said polymer foam material, wherein said primary particles of anode active material have a total solid volume Va, and said pores have a total pore volume Vp, and the volume ratio Vp/Va is from 0.1/1.0 to 10/1.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: May 14, 2024
    Assignee: Honeycomb Battery Company
    Inventors: Yi-jun Lin, Yen-Po Lin, Sheng-Yi Lu, Bor Z. Jang
  • Publication number: 20240139262
    Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.
    Type: Application
    Filed: October 13, 2023
    Publication date: May 2, 2024
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shih-Wei LIN, Yen-Po CHEN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, You-Shan TSAI, Zi-He WU
  • Patent number: 11961998
    Abstract: Provided is a method of producing multiple particulates, the method comprising: (a) dispersing multiple primary particles of an anode active material, having a particle size from 2 nm to 20 ?m, and particles of a polymer foam material, having a particle size from 50 nm to 20 ?m, and an optional adhesive or binder in a liquid medium to form a slurry; and (b) shaping the slurry and removing the liquid medium to form the multiple particulates having a diameter from 100 nm to 50 ?m; wherein at least one of the multiple particulates comprises a polymer foam material having pores and a single or a plurality of the primary particles embedded in or in contact with the polymer foam material, wherein the primary particles have a total solid volume Va, and the pores have a total pore volume Vp, and the volume ratio Vp/Va is from 0.1/1.0 to 10/1.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: April 16, 2024
    Assignee: Honeycomb Battery Company
    Inventors: Yi-Jun Lin, Yen-Po Lin, Sheng-Yi Lu, Bor Z. Jang
  • Publication number: 20240088223
    Abstract: In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.
    Type: Application
    Filed: March 24, 2023
    Publication date: March 14, 2024
    Inventors: Shu-Wen SHEN, Yen-Po Lin, Chun-Han Chen
  • Publication number: 20240021684
    Abstract: A method includes depositing a dummy semiconductor layer and a first semiconductor layer over a substrate, forming spacers on sidewalls of the dummy semiconductor layer, forming a first epitaxial material in the substrate, exposing the dummy semiconductor layer and the first epitaxial material, where exposing the dummy semiconductor layer and the first epitaxial material includes thinning a backside of the substrate, etching the dummy semiconductor layer to expose the first semiconductor layer, where the spacers remain over and in contact with end portions of the first semiconductor layer while etching the dummy semiconductor layer, etching portions of the first semiconductor layer using the spacers as a mask, and replacing a second epitaxial material and the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of a first transistor.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 18, 2024
    Inventors: Yen-Po Lin, Wei-Yang Lee, Yuan-Ching Peng, Chia-Pin Lin, Jiun-Ming Kuo
  • Patent number: 11799002
    Abstract: A method includes depositing a dummy semiconductor layer and a first semiconductor layer over a substrate, forming spacers on sidewalls of the dummy semiconductor layer, forming a first epitaxial material in the substrate, exposing the dummy semiconductor layer and the first epitaxial material, where exposing the dummy semiconductor layer and the first epitaxial material includes thinning a backside of the substrate, etching the dummy semiconductor layer to expose the first semiconductor layer, where the spacers remain over and in contact with end portions of the first semiconductor layer while etching the dummy semiconductor layer, etching portions of the first semiconductor layer using the spacers as a mask, and replacing a second epitaxial material and the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of a first transistor.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Po Lin, Wei-Yang Lee, Yuan-Ching Peng, Chia-Pin Lin, Jiun-Ming Kuo
  • Patent number: 11757018
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an n-type doped region in a semiconductor substrate and forming a semiconductor stack over the semiconductor substrate. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes introducing n-type dopants from the n-type doped region into the semiconductor stack during the forming of the semiconductor stack. The method further includes patterning the semiconductor stack to form a fin structure and forming a dummy gate stack to wrap around a portion of the fin structure. In addition, the method includes removing the dummy gate stack and the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor layers. The method includes forming a metal gate stack to wrap around the semiconductor nanostructures.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-An Yu, Hung-Ju Chou, Jet-Rung Chang, Yen-Po Lin, Jiun-Ming Kuo
  • Patent number: 11715832
    Abstract: Provided is anode active material for use in a lithium ion battery, wherein the anode active material is capable of reversibly storing lithium ions therein up to a maximum lithium storage capacity Cmax during a charge or discharge of the battery and the anode active material comprises an amount of solid-electrolyte interphase (SEI) on a surface or in an internal structure of the anode active material wherein the SEI is pre-formed prior to incorporating the anode active material in an anode electrode of the battery. Also provided is a method of producing the pre-formed SEI substances in the anode material; e.g. through repeated lithiation/delithiation procedures.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: August 1, 2023
    Assignee: Global Graphene Group, Inc.
    Inventors: Yen-Po Lin, Yu-Chan Yen, Yu-Sheng Su, Bor Z. Jang
  • Publication number: 20230238448
    Abstract: A method for fabricating an integrated circuit structure is provided. The method includes forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately arranged over the semiconductor substrate; patterning the epitaxial stack into a first fin and a second fin, wherein from a top view the first fin extends along a first direction, and the second fin has a first fin line extending along the first direction and a second fin line extending along a second direction different from the first direction; forming a first gate structure over a first portion of the first fin; etching a recess in a second portion of the first fin adjacent the first portion of the first fin; and forming a source/drain feature in the recess.
    Type: Application
    Filed: January 27, 2022
    Publication date: July 27, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Jung CHIEN, Jiun-Ming KUO, Shih-Hao FU, Yuan-Ching PENG, Yen-Po LIN
  • Publication number: 20230067804
    Abstract: A plurality of first semiconductor layers and second semiconductor layers are formed over a front side of a substrate. The first semiconductor layers interleave with the second semiconductor layers in a vertical direction. The first semiconductor layers and second semiconductor layers are etched into a plurality of stacks. The etching is performed such that a bottommost first semiconductor layer is etched to have a tapered profile in a cross-sectional view. The bottommost first semiconductor layer is replaced with a dielectric layer. The dielectric layer inherits the tapered profile of the bottommost first semiconductor layer. Gate structures are formed over the stacks. The gate structures each extend in a first horizontal direction. A first interconnect structure is formed over the gate structures. A second interconnect structure is formed over a back side of the substrate.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Shu-Wen Shen, Wei-Yang Lee, Yen-Po Lin, Jiun-Ming Kuo, Kuo-Yi Chao, Yuan-Ching Peng
  • Publication number: 20230062305
    Abstract: A method includes forming a semiconductor substrate, forming hard mask layers (HMs) over the semiconductor substrate, forming first mandrels over the HMs, forming second mandrels along sidewalls of the first mandrels, forming a protective layer over the first mandrels and the second mandrels, removing a portion of the protective layer to expose portions of the first and the second mandrels, removing the exposed portions of the second mandrels with respect to the exposed portions of the first mandrels, removing remaining portions of the protective layer to expose remaining portions of the first and second mandrels, where the exposed portions of the first mandrels and the remaining portions of the first and second mandrels form a mandrel structure, patterning the HMs using the mandrel structure as an etching mask, and patterning the semiconductor substrate to form a fin structure using the patterned HMs as an etching mask.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Jen-Hong Chang, Yuan-Ching Peng, Jiun-Ming Kuo, Kuo-Yi Chao, Chih-Chung Chang, You-Ting LIN, Yen-Po Lin, Chen-Hsuan Liao
  • Publication number: 20230010541
    Abstract: A method includes forming a p-well and an n-well in a substrate. The method further includes forming a stack of interleaving first semiconductor layers and second semiconductor layers over the p-well and the n-well, the first semiconductor layers having a first thickness and the second semiconductor layers having a second thickness different than the first thickness. The method further includes annealing the stack of interleaving semiconductor layers. The method further includes patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well. The method further includes etching to remove the second semiconductor layers from the first and second fin-shaped structures, where the first semiconductor layers have a different thickness within each of the first and second fin-shaped structures after the etching. The method further includes forming a metal gate over the first and second fin-shaped structures.
    Type: Application
    Filed: May 6, 2022
    Publication date: January 12, 2023
    Inventors: Hung-Ju CHOU, Yen-Po LIN, Jiun-Ming KUO, Yuan-Ching PENG
  • Publication number: 20220384605
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an n-type doped region in a semiconductor substrate and forming a semiconductor stack over the semiconductor substrate. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes introducing n-type dopants from the n-type doped region into the semiconductor stack during the forming of the semiconductor stack. The method further includes patterning the semiconductor stack to form a fin structure and forming a dummy gate stack to wrap around a portion of the fin structure. In addition, the method includes removing the dummy gate stack and the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor layers. The method includes forming a metal gate stack to wrap around the semiconductor nanostructures.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-An YU, Hung-Ju CHOU, Jet-Rung CHANG, Yen-Po LIN, Jiun-Ming KUO
  • Publication number: 20210376094
    Abstract: A method includes depositing a dummy semiconductor layer and a first semiconductor layer over a substrate, forming spacers on sidewalls of the dummy semiconductor layer, forming a first epitaxial material in the substrate, exposing the dummy semiconductor layer and the first epitaxial material, where exposing the dummy semiconductor layer and the first epitaxial material includes thinning a backside of the substrate, etching the dummy semiconductor layer to expose the first semiconductor layer, where the spacers remain over and in contact with end portions of the first semiconductor layer while etching the dummy semiconductor layer, etching portions of the first semiconductor layer using the spacers as a mask, and replacing a second epitaxial material and the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of a first transistor.
    Type: Application
    Filed: March 12, 2021
    Publication date: December 2, 2021
    Inventors: Yen-Po Lin, Wei-Yang Lee, Yuan-Ching Peng, Chia-Pin Lin, Jiun-Ming Kuo
  • Patent number: 10965438
    Abstract: A signal receiving circuit, a memory storage device and a signal receiving method are provided. The signal receiving circuit includes an equalizer module, a clock and data recovery (CDR) circuit and a controller. The equalizer module is configured to receive a first signal and compensate the first signal to generate a second signal. The CDR circuit is configured to perform a phase locking on the second signal. The controller is configured to open or close a signal pattern filter of the CDR circuit according to the second signal, wherein the signal pattern filter is configured to filter a signal having a specific pattern in the second signal.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: March 30, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Yang Sun, Sheng-Wen Chen, Yen-Po Lin, Bo-Jing Lin, Po-Min Cheng
  • Publication number: 20210050597
    Abstract: Provided is anode active material for use in a lithium ion battery, wherein the anode active material is capable of reversibly storing lithium ions therein up to a maximum lithium storage capacity Cmax during a charge or discharge of the battery and the anode active material comprises an amount of solid-electrolyte interphase (SEI) on a surface or in an internal structure of the anode active material wherein the SEI is pre-formed prior to incorporating the anode active material in an anode electrode of the battery. Also provided is a method of producing the pre-formed SEI substances in the anode material; e.g. through repeated lithiation/delithiation procedures.
    Type: Application
    Filed: August 12, 2019
    Publication date: February 18, 2021
    Inventors: Yen-Po Lin, Yu-Chan Yen, Yu-Sheng Su, Bor Z. Jang
  • Publication number: 20210013490
    Abstract: Provided is a prelithiated anode active material particle for use in a lithium-ion battery, the particle is capable of reversibly storing lithium ions therein during a charge or discharge of the battery and comprises an amount of lithium from 1% to 100% of a maximum lithium content that can be contained in the anode active material particle, having a first lithium concentration C1 near a particle surface and a second lithium concentration C2 inside the particle and away from the particle surface and wherein C1<C2.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 14, 2021
    Applicant: Nanotek Instruments, Inc.
    Inventors: Yen-Po Lin, Yu-Sheng Su, Bor Z. Jang
  • Publication number: 20200358088
    Abstract: Provided is a method of producing multiple particulates, the method comprising: (a) dispersing multiple primary particles of an anode active material, having a particle size from 2 nm to 20 ?m, and particles of a polymer foam material, having a particle size from 50 nm to 20 ?m, and an optional adhesive or binder in a liquid medium to form a slurry; and (b) shaping the slurry and removing the liquid medium to form the multiple particulates having a diameter from 100 nm to 50 ?m; wherein at least one of the multiple particulates comprises a polymer foam material having pores and a single or a plurality of the primary particles embedded in or in contact with the polymer foam material, wherein the primary particles have a total solid volume Va, and the pores have a total pore volume Vp, and the volume ratio Vp/Va is from 0.1/1.0 to 10/1.
    Type: Application
    Filed: May 6, 2019
    Publication date: November 12, 2020
    Applicant: Nanotek Instruments, Inc.
    Inventors: Yi-jun Lin, Yen-Po Lin, Sheng-Yi Lu, Bor Z. Jang
  • Publication number: 20200358081
    Abstract: Provided is an anode particulate for a lithium battery, the particulate comprising a polymer foam material having pores and a single or a plurality of primary particles of an anode active material embedded in or in contact with said polymer foam material, wherein said primary particles of anode active material have a total solid volume Va, and said pores have a total pore volume Vp, and the volume ratio Vp/Va is from 0.1/1.0 to 10/1.
    Type: Application
    Filed: May 6, 2019
    Publication date: November 12, 2020
    Applicant: Nanotek Instruments, Inc.
    Inventors: Yi-jun Lin, Yen-Po Lin, Sheng-Yi Lu, Bor Z. Jang