Patents by Inventor Yen-Ru LEE
Yen-Ru LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11476331Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.Type: GrantFiled: November 30, 2020Date of Patent: October 18, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chi Tai, Chii-Horng Li, Pei-Ren Jeng, Yen-Ru Lee, Yan-Ting Lin, Chih-Yun Chin
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Publication number: 20220302281Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, an epitaxial region formed in the fin structure and adjacent to the gate structure. The epitaxial region can embed a plurality of clusters of dopants.Type: ApplicationFiled: March 19, 2021Publication date: September 22, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Wei LEE, Chii-Horng LI, Heng-Wen TING, Yee-Chia YEO, Yen-Ru LEE, Chih-Yun CHIN, Chih-Hung NIEN, Jing Yi YAN
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Patent number: 11430878Abstract: A method includes etching a semiconductor substrate to form a plurality of semiconductor fins. The semiconductor fins are etched to form a recess. An epitaxy structure is grown in the recess. The epitaxy structure has a W-shape cross section. A capping layer is formed over the epitaxy structure. The capping layer is at least conformal to a sidewall of the epitaxy structure. The capping layer is etched to expose a top surface of the epitaxy structure. A first portion of the capping layer remains over the sidewall of the epitaxy structure after etching the capping layer. A contact is formed in contact with the exposed top surface of the epitaxy structure and the first portion of the capping layer.Type: GrantFiled: August 14, 2020Date of Patent: August 30, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Lilly Su, Yang-Tai Hsiao
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Publication number: 20220190139Abstract: A method for forming a semiconductor structure includes forming a gate structure over a substrate. The method also includes forming a spacer on a sidewall of the gate structure. The method also includes forming a source/drain recess beside the spacer. The method also includes treating the source/drain recess and partially removing the spacers in a first cleaning process. The method also includes treating the source/drain recess with a plasma process after performing the first cleaning process. The method also includes treating the source/drain recess in a second cleaning process after treating the source/drain recess with the plasma process. The method also includes forming a source/drain structure in the source/drain recess after performing the second cleaning process.Type: ApplicationFiled: March 7, 2022Publication date: June 16, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Wei LEE, Yen-Ru LEE, Hsueh-Chang SUNG, Yee-Chia YEO
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Publication number: 20220123117Abstract: Embodiments provide a way of treating source/drain recesses with a high heat treatment and an optional hydrogen plasma treatment. The high heat treatment smooths the surfaces inside the recesses and remove oxides and etching byproducts. The hydrogen plasma treatment enlarges the recesses vertically and horizontally and inhibits further oxidation of the surfaces in the recesses.Type: ApplicationFiled: January 3, 2022Publication date: April 21, 2022Inventors: Chien-Wei Lee, Hsueh-Chang Sung, Yen-Ru Lee
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Patent number: 11271096Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes forming a source/drain recess adjacent to the gate structure. The method also includes wet cleaning the source/drain recess in a first wet cleaning process. The method also includes treating the source/drain recess with a plasma process. The method also includes wet cleaning the source/drain recess in a second wet cleaning process after treating the source/drain recess via the plasma process. The method also includes growing a source/drain epitaxial structure in the source/drain recess.Type: GrantFiled: April 1, 2020Date of Patent: March 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Wei Lee, Yen-Ru Lee, Hsueh-Chang Sung, Yee-Chia Yeo
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Patent number: 11264237Abstract: A transistor is provided including a source-drain region, the source-drain region including a first layer wherein a first average silicon content is between about 80% and 100%, a second layer wherein a second average silicon content is between zero and about 90%, the second average silicon content being smaller than the first average silicon content by at least 7%, and the second layer disposed on and adjacent the first layer, a third layer wherein a third average silicon content is between about 80% and 100%, and a fourth layer wherein a fourth average silicon content is between zero and about 90%, the fourth average silicon content being smaller than the third average silicon content by at least 7%, and the fourth layer disposed on and adjacent the third layer.Type: GrantFiled: July 2, 2019Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yun Chin, Tzu-Hsiang Hsu, Yen-Ru Lee, Chii-Horng Li
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Publication number: 20220059655Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.Type: ApplicationFiled: November 8, 2021Publication date: February 24, 2022Inventors: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin
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Patent number: 11257951Abstract: A method of manufacturing a semiconductor device includes forming a first gate stack over a substrate. The method further includes etching the substrate to define a cavity. The method further includes growing a first epitaxial (epi) material in the cavity, wherein the first epi material includes a first upper surface having a first crystal plane. The method further includes growing a second epi material on the first epi material, wherein the second epi material includes a second upper surface having the first crystal plane. The method further includes treating the second epi material, wherein treating the second epi material comprises causing the second upper surface to transform to a second crystal plane different from the first crystal plane.Type: GrantFiled: November 4, 2020Date of Patent: February 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lilly Su, Chii-Horng Li, Ming-Hua Yu, Pang-Yen Tsai, Tze-Liang Lee, Yen-Ru Lee
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Patent number: 11217672Abstract: Embodiments provide a way of treating source/drain recesses with a high heat treatment and an optional hydrogen plasma treatment. The high heat treatment smooths the surfaces inside the recesses and remove oxides and etching byproducts. The hydrogen plasma treatment enlarges the recesses vertically and horizontally and inhibits further oxidation of the surfaces in the recesses.Type: GrantFiled: November 8, 2019Date of Patent: January 4, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Wei Lee, Hsueh-Chang Sung, Yen-Ru Lee
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Publication number: 20210391456Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium conType: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Inventors: Kun-Mu Li, Heng-Wen Ting, Yen-Ru Lee, Hsueh-Chang Sung
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Publication number: 20210351081Abstract: A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin.Type: ApplicationFiled: July 22, 2021Publication date: November 11, 2021Inventors: Kun-Mu Li, Heng-Wen Ting, Hsueh-Chang Sung, Yen-Ru Lee, Chien-Wei Lee
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Patent number: 11171209Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.Type: GrantFiled: August 22, 2019Date of Patent: November 9, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin
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Publication number: 20210336048Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.Type: ApplicationFiled: July 9, 2021Publication date: October 28, 2021Inventors: Chien-Wei Lee, Hsueh-Chang Sung, Yen-Ru Lee, Jyun-Chih Lin, Tzu-Hsiang Hsu, Feng-Cheng Yang
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Publication number: 20210313443Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes forming a source/drain recess adjacent to the gate structure. The method also includes wet cleaning the source/drain recess in a first wet cleaning process. The method also includes treating the source/drain recess with a plasma process. The method also includes wet cleaning the source/drain recess in a second wet cleaning process after treating the source/drain recess via the plasma process. The method also includes growing a source/drain epitaxial structure in the source/drain recess.Type: ApplicationFiled: April 1, 2020Publication date: October 7, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Wei LEE, Yen-Ru LEE, Hsueh-Chang SUNG, Yee-Chia YEO
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Patent number: 11133416Abstract: In an embodiment, a device includes: a fin extending from a substrate; a gate stack over a channel region of the fin; and a source/drain region in the fin adjacent the channel region, the source/drain region including: a first epitaxial layer contacting sidewalls of the fin, the first epitaxial layer including silicon and germanium doped with a dopant, the first epitaxial layer having a first concentration of the dopant; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and germanium doped with the dopant, the second epitaxial layer having a second concentration of the dopant, the second concentration being greater than the first concentration, the first epitaxial layer and the second epitaxial layer having a same germanium concentration.Type: GrantFiled: August 23, 2019Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yan-Ting Lin, Hsueh-Chang Sung, Yen-Ru Lee
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Patent number: 11121255Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.Type: GrantFiled: May 11, 2020Date of Patent: September 14, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chii-Horng Li, Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin
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Patent number: 11107923Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium conType: GrantFiled: June 14, 2019Date of Patent: August 31, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kun-Mu Li, Heng-Wen Ting, Yen-Ru Lee, Hsueh-Chang Sung
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Publication number: 20210265195Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Li-Li Su, Chien-Chang Su, Heng-Wen Ting, Jung-Chi Tai, Che-Hui Lee, Ying-Wei Li
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Publication number: 20210265350Abstract: A method includes forming first devices in a first region of a substrate, wherein each first device has a first number of fins; forming second devices in a second region of the substrate that is different from the first region, wherein each second device has a second number of fins that is different from the first number of fins; forming first recesses in the fins of the first devices, wherein the first recesses have a first depth; after forming the first recesses, forming second recesses in the fins of the second devices, wherein the second recesses have a second depth different from the first depth; growing a first epitaxial source/drain region in the first recesses; and growing a second epitaxial source/drain region in the second recess.Type: ApplicationFiled: December 21, 2020Publication date: August 26, 2021Inventors: Chih-Yun Chin, Yen-Ru Lee, Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Heng-Wen Ting, Chii-Horng Li, Yee-Chia Yeo