Abstract: An extreme ultra violet (EUV) radiation source apparatus includes a collector mirror, a target droplet generator for generating a tin (Sn) droplet, a rotatable debris collection device, one or more coils for generating an inductively coupled plasma (ICP), a gas inlet for providing a source gas for the ICP, and a chamber enclosing at least the collector mirror and the rotatable debris collection device. The gas inlet and the one or more coils are configured such that the ICP is spaced apart from the collector mirror.

Abstract: A method of controlling an extreme ultraviolet (EUV) lithography system is disclosed. The method includes irradiating a target droplet with EUV radiation, detecting EUV radiation reflected by the target droplet, determining aberration of the detected EUV radiation, determining a Zernike polynomial corresponding to the aberration, and performing a corrective action to reduce a shift in Zernike coefficients of the Zernike polynomial.

Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

Abstract: Techniques and examples of hybrid automatic repeat request (HARQ) buffer size design for communication systems are described. A user equipment (UE) communicates with a serving cell of a wireless network using a HARQ mechanism, with the communicating involving: (a) determining, by the processor, a respective size of each buffer of a plurality of buffers corresponding to a plurality of HARQ processes on a per-HARQ process basis; and (b) storing, by the processor, respective information in each buffer of the plurality of buffers for a corresponding HARQ process among the plurality of HARQ processes.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: A method of wireless communication of a UE is provided. The UE determines resources of a first PDSCH and resources of second at least one PDSCH on a cell, the first PDSCH being a unicast PDSCH specific to the UE. The UE determines that the first PDSCH overlaps with the second at least one PDSCH in a time domain. The UE determines whether the second at least one PDSCH is another unicast PDSCH specific to the UE. When the second at least one PDSCH is not another unicast PDSCH specific to the UE, a duration required for decoding the first PDSCH meets a duration threshold, and the cell is in a first frequency range, the UE (a) refrains from decoding the first PDSCH independently of a transport block size of the second at least one PDSCH or (b) determines a transport block size of the second at least one PDSCH.

Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.

Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

Abstract: An apparatus determines a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding. The apparatus compares the CBS with at least one threshold, determines, based on a result of the comparison, a Kb number and determines a Kp number based on a code rate and the Kb number. The apparatus generates a parity check matrix. An information portion of the parity check matrix is a first matrix formed by M number of second square matrices. M is equal to Kp multiplied by Kb. A total number of columns in the Kb number of second square matrices is equal to a total number of bits of the CBS. One or more matrices of the M number of second square matrices are circular permutation matrices. The apparatus operates an LDPC encoder or an LDPC decoder based on the parity check matrix.

Abstract: An efficient Hybrid Automatic Repeat Request (HARQ) operation for low-latency and high-performance services in one radio access technology (RAT) in a wireless communication network is proposed. Under the proposed single HARQ operation scheme, an adaptive HARQ-ACK feedback timing is applied based on UE conditions and UE capability to support the tradeoff between low-latency and high-performance applications. In one embodiment, UE signals the network its HARQ-ACK timing capability. Furthermore, an adaptive number of HARQ processes is applied with a fixed HARQ soft buffer size because the hardware cost for HARQ soft buffer does not linearly increase with the number of HARQ processes. In one embodiment, UE determines a nominal HARQ soft buffer size and HARQ soft buffer size for each HARQ process based on a network-configured HARQ process number.

Abstract: Concepts and schemes pertaining to structure of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide encoded data. A transceiver of the apparatus transmits the encoded data to at least one network node of a wireless network. In encoding the data to provide the encoded data, the processor encodes the data to result in each code block in the encoded data comprising a respective bit-level interleaver.

Abstract: Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits.

Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

Abstract: Concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code are described. A processor of an apparatus may generate a quasi-cyclic-low-density parity-check (QC-LDPC) code and encode data using the selected codebook. In generating the QC-LDPC code, the processor may define a plurality of sets of lifting factors, generate a respective table of shift values for each lifting factor of the plurality of sets of lifting factors, and generate the QC-LDPC code using a base matrix and the shift coefficient table.

Abstract: A processor of an apparatus selects a codebook from a plurality of codebooks embedded in a quasi-cyclic-low-density parity-check (QC-LDPC) code. The processor stores the selected codebook in a memory associated with the processor. The processor also encodes data using the selected codebook to generate a plurality of modulation symbols of the data. The processor further controls a transmitter of the apparatus to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus. In selecting the codebook from the plurality of codebooks embedded in the QC-LDPC code, the processor selects the codebook according to one or more rules such that a small codebook requiring a shorter amount of processing latency for the encoding is selected for the encoding unless a larger codebook corresponding to a larger amount of processing latency for the encoding is necessary for the encoding.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: A method of wireless communication of a UE is provided. The UE determines resources of a first PDSCH and resources of second at least one PDSCH on a cell, the first PDSCH being a unicast PDSCH specific to the UE. The UE determines that the first PDSCH overlaps with the second at least one PDSCH in a time domain. The UE determines whether the second at least one PDSCH is another unicast PDSCH specific to the UE. When the second at least one PDSCH is not another unicast PDSCH specific to the UE, a duration required for decoding the first PDSCH meets a duration threshold, and the cell is in a first frequency range, the UE (a) refrains from decoding the first PDSCH independently of a transport block size of the second at least one PDSCH or (b) determines a transport block size of the second at least one PDSCH.

Abstract: Techniques and examples of hybrid automatic repeat request (HARQ) buffer size design for communication systems are described. A user equipment (UE) communicates with a serving cell of a wireless network using a HARQ mechanism, with the communicating involving: (a) determining, by the processor, a respective size of each buffer of a plurality of buffers corresponding to a plurality of HARQ processes on a per-HARQ process basis; and (b) storing, by the processor, respective information in each buffer of the plurality of buffers for a corresponding HARQ process among the plurality of HARQ processes.

Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer.