Patents by Inventor Yen-Ting Lin
Yen-Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240154447Abstract: A power system including a first battery pack, a second battery pack, and a power management circuit is disclosed. The first battery pack has a first end and a second end, and has a first battery capacity. The second battery pack has a third end and a fourth end. The third end is coupled to the second end of the first battery pack and provides a low battery voltage. The fourth end is grounded, the second battery pack has a second battery capacity, and the second battery capacity is greater than the first battery capacity. The power management circuit is coupled to the second battery pack to receive the low battery voltage, and provides a component operating voltage to an electronic components based on the low battery voltage.Type: ApplicationFiled: August 29, 2023Publication date: May 9, 2024Applicant: PEGATRON CORPORATIONInventors: Yi-Hsuan Lee, Liang-Cheng Kuo, Chun-Wei Ko, Ya Ju Cheng, Chih Wei Huang, Ywh Woei Yeh, Yu Cheng Lin, Yen Ting Wang
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Publication number: 20240153993Abstract: Semiconductor devices and methods of fabrication are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin and into a substrate as an initial step in forming a source/drain region. A first semiconductor material is epitaxially grown from channels exposed along sidewalls of the opening to form first source/drain structures. A second semiconductor material is epitaxially grown from the first semiconductor material to form a second source/drain structure over and to fill a space between the first source/drain structures. A bottom of the second source/drain structure is located below a bottommost surface of the first source/drain structures. The second semiconductor material has a greater concentration percentage by volume of germanium than the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Inventors: Yen-Ting Chen, Po-Shao Lin, Wei-Yang Lee
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Publication number: 20240134256Abstract: A projection device includes a shell, a lens, two first ribs, two second ribs, and a sliding cover. The shell has a top plate, a left sidewall, and a right sidewall, the top plate is respectively connected to the left sidewall and the right sidewall, and the top plate has an opening. The lens is disposed in the shell and exposed by the opening. The two first ribs are disposed on the top plate, extending directions of the two first ribs are perpendicular to the left sidewall and the right sidewall, and the opening is disposed between the two first ribs. The sliding cover is slidably disposed on the shell for covering the opening. The two second ribs are disposed on a top cover body of the sliding cover, and one of the two second ribs is located between the two first ribs.Type: ApplicationFiled: October 23, 2023Publication date: April 25, 2024Applicant: Coretronic CorporationInventors: Wei-Min Chien, Yen-Ting Lin, Yao-Hung Chen
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Patent number: 11968843Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.Type: GrantFiled: February 7, 2019Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Te Lin, Yen-Chung Ho, Pin-Cheng Hsu, Han-Ting Tsai, Katherine Chiang
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Publication number: 20240096958Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Jung-Chi Tai, Chii-Horng Li, Pei-Ren Jeng, Yen-Ru Lee, Yan-Ting Lin, Chih-Yun Chin
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Publication number: 20240077914Abstract: A foldable electronic device includes a first body having an end and a first inclined surface, a second body having a second inclined surface, and a hinge module. The end includes an accommodating area. A virtual shaft line exists between sides of the first inclined surface and the second inclined surface that are closest to each other. The second body rotates relative to the first body through the virtual shaft line. The hinge module includes a first bracket adjacent to the first inclined surface, connected to the first body, and located in the accommodating area, a second bracket adjacent to the second inclined surface and connected to the second body, and a third bracket including a first end and a second end. The first bracket is connected to the first end through a first torsion assembly. The second bracket is connected to the second end through a second torsion assembly.Type: ApplicationFiled: April 27, 2023Publication date: March 7, 2024Applicant: ASUSTeK COMPUTER INC.Inventors: Chih-Han Chang, Tsung-Ju Chiang, Chi-Hung Lin, Yen-Ting Liu
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Publication number: 20240081081Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.Type: ApplicationFiled: January 10, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Ling Lee, Chung-Te Lin, Han-Ting Tsai, Wei-Gang Chiu, Yen-Chieh Huang, Ming-Yi Yang
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Patent number: 11914429Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.Type: GrantFiled: March 9, 2023Date of Patent: February 27, 2024Assignee: Acer IncorporatedInventors: Hung-Chi Chen, Shun-Bin Chen, Huei-Ting Chuang, Yen-Chieh Chiu, Yu-Wen Lin, Yen-Chou Chueh, Po-Yi Lee
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Publication number: 20240055048Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.Type: ApplicationFiled: July 31, 2023Publication date: February 15, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
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Publication number: 20230377614Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.Type: ApplicationFiled: July 24, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Qing Dong, Mahmut Sinangil, Yen-Ting Lin, Kerem Akarvardar, Carlos H. Diaz, Yih Wang
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Publication number: 20230354585Abstract: Methods, apparatuses, and systems related to a digit line and cell contact are described. An example apparatus includes a semiconductor structure comprising a first layer comprising a first material on sidewalls of a plurality of patterned material. The apparatus further includes a second layer comprising a nitride material on sidewalls of the first layer. The apparatus further includes a third layer comprising the first material on sidewalls of the second layer. The apparatus further includes a base area, to provide digit line and cell contact isolation for the semiconductor structure. The apparatus further includes an active area, adjacent to the base area, that is adjacent to the semiconductor structure.Type: ApplicationFiled: April 28, 2022Publication date: November 2, 2023Inventors: Albert P. Chan, Sanjeev Sapra, Vivek Yadav, Yen Ting Lin, Devesh Dadhich Shreeram
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Patent number: 11776867Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 ?m and 300 ?m. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.Type: GrantFiled: June 14, 2022Date of Patent: October 3, 2023Assignee: Industrial Technology Research InstituteInventors: Kuo-Shu Kao, Tao-Chih Chang, Wen-Chih Chen, Tai-Jyun Yu, Po-Kai Chiu, Yen-Ting Lin, Wei-Kuo Han
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Patent number: 11763882Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.Type: GrantFiled: July 25, 2022Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
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Patent number: 11735235Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.Type: GrantFiled: January 7, 2022Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Qing Dong, Mahmut Sinangil, Yen-Ting Lin, Kerem Akarvardar, Carlos H. Diaz, Yih Wang
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THERMOPLASTIC COMPOSITION, THERMOPLASTIC COMPOSITE, AND METHOD FOR PRODUCING THERMOPLASTIC COMPOSITE
Publication number: 20230174784Abstract: The present invention relates to a thermoplastic composition, a thermoplastic composite, and a method for producing the thermoplastic composite. In the method for producing the thermoplastic composite, a polymer, an acid-modified lignin with a specific element content and a compatibilizer with a specific melt flow index and a specific maleic anhydride content are used to produce the thermoplastic composite. Hydroxy groups of the acid-modified lignin react with maleic anhydride groups of the compatibilizer to generate ester bonds via an in-situ reaction catalyzed by acidic groups of the acid-modified lignin to enhance compatibility between the polymer and the lignin, thereby increasing a mechanical strength of the resulted thermoplastic composite.Type: ApplicationFiled: November 29, 2022Publication date: June 8, 2023Inventors: Kwang-Ming CHEN, Jung-Hung KAO, Kun-Pei HSIEH, Chao-Shun CHANG, Yen-Ting LIN, Hung-Jue SUE -
Publication number: 20220359001Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
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Publication number: 20220310473Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 ?m and 300 ?m. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.Type: ApplicationFiled: June 14, 2022Publication date: September 29, 2022Applicant: Industrial Technology Research InstituteInventors: Kuo-Shu Kao, Tao-Chih Chang, Wen-Chih Chen, Tai-Jyun Yu, Po-Kai Chiu, Yen-Ting Lin, Wei-Kuo Han
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Patent number: 11404114Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.Type: GrantFiled: October 12, 2020Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
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Patent number: 11397593Abstract: Loadable BIOS preset configurations are disclosed, permitting large numbers of BIOS settings to be quickly implemented through the use of hot-keys. In an in-band process, the BIOS can be updated locally by pressing a hot-key to load a preset configuration of BIOS settings. The preset configuration can be stored by accessing a BIOS setup utility, selecting updated BIOS settings, and assigning a hot-key. In an out-of-band process, a system's BIOS can be updated remotely by sending a hot-key selection to use in a subsequent boot-up via a Future BIOS Settings variable, then sending the configuration information as a UEFI variable. When the remote computer next boots, the Future BIOS Settings variable will be used to simulate a hot-key selection that will cause the system to apply the configuration information in the UEFI variable.Type: GrantFiled: March 19, 2021Date of Patent: July 26, 2022Assignee: QUANTA COMPUTER INC.Inventor: Yen-Ting Lin
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Patent number: D976852Type: GrantFiled: June 18, 2020Date of Patent: January 31, 2023Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Sheng-Tsai Wu, Hsin-Han Lin, Yuan-Yin Lo, Kuo-Shu Kao, Tai-Jyun Yu, Han-Lin Wu, Yen-Ting Lin