Abstract: The present invention provides a photodiode structure, which includes a chip, an electrode group, an electrode protection layer and a metal alloy band-pass optical film. The electrode group is arranged on the chip, and the electrode group includes a positive electrode and a negative electrode; the electrode protection layer is arranged on the chip and covers the electrode group; the metal alloy band-pass optical film is arranged on the electrode protection layer and includes a plurality of layered structures, and the plurality of layered structures includes at least two metal alloy material layers.

Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.

Abstract: A memory unit includes at least one memory cell and a computational cell. The at least one memory cell stores a weight. The at least one memory cell is controlled by a first word line and includes a local bit line transmitting the weight. The computational cell is connected to the at least one memory cell and receiving the weight via the local bit line. Each of an input bit line and an input bit line bar transmits a multi-bit input value. The computational cell is controlled by a second word line and an enable signal to generate a multi-bit output value on each of an output bit line and an output bit line bar according to the multi-bit input value multiplied by the weight. The computational cell is controlled by a first switching signal and a second switching signal for charge sharing.

Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.

Abstract: An electrical connector assembly includes: a bracket; and at least one transmission assembly mounted to the bracket and including an internal printed circuit board (PCB), a board-mount connector connected to a first row of conductive pads disposed at a bottom end portion of the PCB, and a plug-in connector connected to a second row of conductive pads disposed at a front end portion of the PCB, wherein the PCB has a third row of conductive pads disposed at a rear end portion thereof.

Abstract: In a method of forming a heat dissipating structure for a semiconductor chip, a soldering material is disposed on a top surface of the semiconductor chip. A first region of metal plating is formed on a surface of a lid. The first region has a first width and a first length. The first width is larger than a second width of the top surface of the semiconductor chip and the first length is larger than a second length of the top surface of the semiconductor chip. The lid is placed over the semiconductor chip so that the first region of metal plating of the lid is disposed over the soldering material to bond the lid to the semiconductor chip by a soldering material layer having an inverted trapezoidal shape between the lid and the top surface of the semiconductor chip.

Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.

Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.