Abstract: In a method for continuing a function induced by a multi-touch gesture on a touchpad, the object number of the multi-touch gesture is monitored during the function is performed, if the object number is detected changed so that one or more objects are still on the touchpad, the objects left on the touchpad will be detected to identify whether one or more of them move clockwise or anticlockwise, and if a clockwise or anticlockwise movement is detected, the function will be continued.

Abstract: A touchpad is defined with two or more detect regions thereon, and each of the defined detect regions has a respective remiss threshold for identifying remiss touch. When any of the defined detect regions is touched, the touchpad compares the touch area of the detected touch with the remiss threshold of the touched detect region to identify whether the detected touch is a remiss touch or not. Preferably, the location, range and threshold setting of the detect region is user defined, so that a user may adjust the remiss setting for optimized prevention against remiss touch.

Abstract: A virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO unit is provided. In the virtual FIFO DMA device, a DMA unit is for transferring data between the UART unit and the virtual FIFO unit. A virtual FIFO controller, which has a read pointer and a write pointer, is electrically connected with the DMA unit. When the DMA unit reads data from or writes data into the virtual FIFO unit, the virtual FIFO controller correspondingly changes the value of the read pointer or the write pointer. A virtual port is electrically connected to the DMA unit and the processor. A processor reads data from or writes data into the virtual FIFO unit via the virtual port and the DMA unit.

Abstract: A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.

Abstract: A graphics processing system is provided. The graphics processing system comprises a display unit, a frame buffer, an interface, and a controller. The frame buffer, defined by an initial pointer and a boundary pointer first image data in the frame buffer, stores first image data corresponding to a first image area displayed on the display unit. The interface receives a scrolling request directing the first image to scroll in a vertical and/or horizontal direction. The controller determines a reading pointer of the frame buffer according to the initial and boundary pointers and the scrolling request, loads new image data into a memory location at which a particular part of the first image data is stored.

Abstract: A memory system is provided. A processor provides a data access address. A memory device includes a predetermined number of ways. The processor selectively configures a selected number less than or equal to the predetermined number of the ways as cache memory belonging to a cacheable region, and configures remaining ways as directly addressable memory belonging to a directly addressable region by memory configuration information. A memory controller determines the data access address corresponding to the cacheable region or the directly addressable region, selects only the way in the directly addressable region corresponding to the data access address when the data access address corresponds to the directly addressable region, and selects only the way(s) belonging to the cacheable region when the data access address corresponds to the cacheable region. A configuration controller monitors the status of the ways and adjusting the memory configuration information according to the status of the ways.

Abstract: A memory system is described. A processor provides a data access address, and selectively configures a selected number of the ways of a memory device as cache memory belonging to a cacheable region, and configures remaining ways as directly addressable memory belonging to a directly addressable region by the memory configuration information stored in control registers. A cache hit detection circuit includes an address register storing the data access address, tag memories storing tag data of the data access address, a data processing device selectively outputting the tag data or an adjusted tag data as processed data according to a direct address signal, and address comparators each comparing the processed data with portion bits of the data access address from the address register, and outputting an address match signal as comparison match. The tag data is adjusted to a predetermined address by the data processing device, which is the highest address of memory space of the processor.

Abstract: A bicycle has multiple electrical devices and a front and rear wheel assembly, each having a fork with two tines and a wheel with an inner support structure. Moreover, at least one generator is mounted on the wheel assemblies. Each generator has multiple coil devices and multiple permanent magnets. The coil devices are mounted on the tines of at least one fork. The permanent magnets are mounted on the inner support structure of at least one wheel, correspond to and align with the coil devices and generate an electrical current in the coil devices when the wheel rotate. Since no frictional forces are required to drive the generator, the efficiency is higher, and the operation of the bicycle does not interfered by the generator.

Abstract: The present invention discloses an object-detection method and a multi-class Bhattacharyya Boost algorithm used therein, wherein firstly, integral images are calculated from an image data in order to speed up the extraction of the characteristics of the objects; then, multiple rectangles of different sizes are scanned at different locations of the image data, and the multi-class Bhattacharyya Boost algorithm is used to detect multi-class objects. In the present invention, the detection framework can use only one single boosted cascade to determine the status and position of the object inside the image data. The simultaneous multi-class detection of the present invention can effectively overcome the detection difficulties resulting from the diversification of object appearances under different conditions.

Abstract: A transmission circuit for realizing a rate adaptation layer of a digital communication system. The transmission circuit includes a processor and a format conversion circuit. The processor is capable of managing transmission rates of input and output digital signals of the digital communication system. The format conversion circuit includes a plurality of input units and output units; each input unit is for receiving a bit according to the input digital signal, and each output unit is for transmitting a bit to form the output signal. Each input unit and output unit are connected by hardware wires to realize data formatting such as bit-reordering, command insertion.

Abstract: A system clock switching apparatus, which includes a clock source for providing a reference clock signal; a frequency divider electrically connected to the clock source for dividing the reference clock signal to produce a frequency-divided signal and a system clock signal; and an enable signal generator electrically connected to the frequency divider for dividing the frequency-divided signal to produce at least one enable signal. The frequency divider switches the frequency of the system clock signal at a time period corresponding to a pulse edge of the frequency-divided signal.

Abstract: An apparatus and method for adjusting display-related setting of an electronic device are disclosed. The apparatus includes an image sensing device, an image signal processing unit, and a determination device. The image sensing device is for capturing a number of images according to a number of exposure time values and outputting image signals accordingly. The image signal processing unit is coupled to the image sensing device for processing the image signals and outputting a number of image luminance values accordingly. The processor is coupled to the image signal processing unit for adjusting the display-related setting of the electronic device according to the image luminance values and exposure time values.

Abstract: An apparatus for image capturing includes a sensing device, an image processing unit, an image scaling unit, and a memory device. The sensing device is for capturing an image, and the image processing unit is for processing the image. The memory device is for storing the portion of the image, and the image scaling unit is for scaling the portion of the image. After the image processing unit processes the image, only the portion of the image is stored in the memory device to be transmitted to the image scaling unit for image scaling.

Abstract: A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.

Abstract: The present invention provides an overlay mark for aligning different layers on a semiconductor wafer. The overlay mark comprises a bar-in-bar mark and two bar sets on the semiconductor wafer. The bar-in-bar mark comprises an inner bar mark positioned in one of the pre-layer and an outer bar mark positioned in the other pre-layer. The two bar sets are perpendicular to each other, and each of two bar sets comprises two parallel bars. The bars can be connected and the lengths of the bars can be the same or different.

Abstract: A virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO unit is provided. In the virtual FIFO DMA device, a DMA unit is for transferring data between the UART unit and the virtual FIFO unit. A virtual FIFO controller, which has a read pointer and a write pointer, is electrically connected with the DMA unit. When the DMA unit reads data from or writes data into the virtual FIFO unit, the virtual FIFO controller correspondingly changes the value of the read pointer or the write pointer. A virtual port is electrically connected to the DMA unit and the processor. A processor reads data from or writes data into the virtual FIFO unit via the virtual port and the DMA unit.

Abstract: The present invention discloses an object-detection method and a multi-class Bhattacharyya Boost algorithm used therein, wherein firstly, integral images are calculated from an image data in order to speed up the extraction of the characteristics of the objects; then, multiple rectangles of different sizes are scanned at different locations of the image data, and the multi-class Bhattacharyya Boost algorithm is used to detect multi-class objects. In the present invention, the detection framework can use only one single boosted cascade to determine the status and position of the object inside the image data. The simultaneous multi-class detection of the present invention can effectively overcome the detection difficulties resulting from the diversification of object appearances under different conditions.

Abstract: A memory system includes a processor providing a data access address; a set of control registers storing memory configuration information; a memory device comprising a first predetermined number of ways, the processor selectively configuring a selected number less than or equal to the first predetermined number of the ways as cache memory belonging to a cacheable region, and configuring remaining ways as directly addressable memory belonging to a directly addressable region by the memory configuration information; and a memory controller determining the data access address corresponding to the cacheable region or the directly addressable region, selecting only the way in the directly addressable region corresponding to the data access address when the data access address corresponds to the directly addressable region, and selecting only the way(s) belonging to the cacheable region when the data access address corresponds to the cacheable region.

Abstract: A system clock switching apparatus, which includes a clock source for providing a reference clock signal; a frequency divider electrically connected to the clock source for dividing the reference clock signal to produce a frequency-divided signal and a system clock signal; and an enable signal generator electrically connected to the frequency divider for dividing the frequency-divided signal to produce at least one enable signal. The frequency divider switches the frequency of the system clock signal at a time period corresponding to a pulse edge of the frequency-divided signal.

Abstract: A virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO is provided. In the virtual FIFO DMA device, a DMA unit is for transferring data between the UART unit and the virtual FIFO. A virtual FIFO controller, which has a read pointer and a write pointer, is electrically connected with the DMA unit. When the DMA unit reads data from or saves data into the virtual FIFO, the virtual FIFO controller correspondingly changes the value of the read pointer or the write pointer. A virtual port is electrically connected with the DMA unit and the processor respectively. A processor reads data from or writes data into the virtual FIFO via the virtual port and the DMA unit.