Patents by Inventor Yenting Wen
Yenting Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11417598Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.Type: GrantFiled: April 20, 2020Date of Patent: August 16, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Yenting Wen, George Chang
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Patent number: 10811598Abstract: A sensor package includes a semiconductor die including at least one current sensor. The semiconductor die includes a first pass through hole extending from one side of the semiconductor die to an opposite side of the semiconductor die. The semiconductor package further includes a second pass through hole extending from one side of the sensor package to an opposite side of the sensor package. The second pass through hole is aligned with the first pass through hole and is configured to receive a current-carrying conductor. The at least one current sensor senses current flow in the current-carrying conductor received in the second pass through hole. An end of the current-carrying conductor is coupled to a terminal on a circuit board in the sensor package.Type: GrantFiled: February 19, 2020Date of Patent: October 20, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jefferson W. Hall, Michael J. Seddon, Yenting Wen
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Publication number: 20200251413Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.Type: ApplicationFiled: April 20, 2020Publication date: August 6, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng LIN, Yenting WEN, George CHANG
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Publication number: 20200185600Abstract: A semiconductor package includes a semiconductor die. A through hole in the semiconductor package and semiconductor die extends from one side of the semiconductor package and die to an opposite side of the semiconductor package and die. The through hole is configured to receive a current-carrying conductor there through. At least one current sensor is formed in, or on, the semiconductor die and configured to sense current flow in the current-carrying conductor received in the through hole.Type: ApplicationFiled: February 19, 2020Publication date: June 11, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jefferson W. HALL, Michael J. SEDDON, Yenting WEN
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Patent number: 10651124Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.Type: GrantFiled: April 3, 2019Date of Patent: May 12, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Yenting Wen, George Chang
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Publication number: 20200066970Abstract: A semiconductor package includes a semiconductor die. A through hole in the semiconductor package and semiconductor die extends from one side of the semiconductor package and die to an opposite side of the semiconductor package and die. The through hole is configured to receive a current-carrying conductor there through. At least one current sensor is formed in, or on, the semiconductor die and configured to sense current flow in the current-carrying conductor received in the through hole.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jefferson W. HALL, Michael J. SEDDON, Yenting WEN
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Patent number: 10573803Abstract: A semiconductor package includes a semiconductor die. A through hole in the semiconductor package and semiconductor die extends from one side of the semiconductor package and die to an opposite side of the semiconductor package and die. The through hole is configured to receive a current-carrying conductor there through. At least one current sensor is formed in, or on, the semiconductor die and configured to sense current flow in the current-carrying conductor received in the through hole.Type: GrantFiled: August 21, 2018Date of Patent: February 25, 2020Assignee: Semiconductor Components Industries, LLCInventors: Jefferson W. Hall, Michael J. Seddon, Yenting Wen
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Patent number: 10396028Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.Type: GrantFiled: May 8, 2018Date of Patent: August 27, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Yenting Wen, George Chang
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Publication number: 20190229052Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.Type: ApplicationFiled: April 3, 2019Publication date: July 25, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng LIN, Yenting WEN, George CHANG
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Publication number: 20180254243Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.Type: ApplicationFiled: May 8, 2018Publication date: September 6, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng LIN, Yenting WEN, George CHANG
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Publication number: 20180211939Abstract: Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically conductive elements, and at least partially encapsulating the first die and electrically conductive elements in a first mold layer. A first redistribution layer (RDL) is placed over the first mold layer and electrically coupled with the first die. A second die is coupled with the first RDL, and the second die and first RDL are at least partially encapsulated in a second mold layer. A second RDL is formed over the second mold layer and is electrically coupled with the second die. A third mold layer at least partially encapsulates the second RDL. A portion of the substrate is removed to expose (and a solder mask is applied to) surfaces of the electrically conductive elements and of the first mold layer to form a stacked embedded package.Type: ApplicationFiled: March 20, 2018Publication date: July 26, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng LIN, Francis J. CARNEY, Yenting WEN, Chee Hiong CHEW, Azhar ARIPIN
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Patent number: 9984968Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.Type: GrantFiled: June 30, 2016Date of Patent: May 29, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Yenting Wen, George Chang
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Patent number: 9941257Abstract: Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically conductive elements, and at least partially encapsulating the first die and electrically conductive elements in a first mold layer. A first redistribution layer (RDL) is placed over the first mold layer and electrically coupled with the first die. A second die is coupled with the first RDL, and the second die and first RDL are at least partially encapsulated in a second mold layer. A second RDL is formed over the second mold layer and is electrically coupled with the second die. A third mold layer at least partially encapsulates the second RDL. A portion of the substrate is removed to expose (and a solder mask is applied to) surfaces of the electrically conductive elements and of the first mold layer to form a stacked embedded package.Type: GrantFiled: June 2, 2017Date of Patent: April 10, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Francis J. Carney, Yenting Wen, Chee Hiong Chew, Azhar Aripin
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Publication number: 20180033777Abstract: Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically conductive elements, and at least partially encapsulating the first die and electrically conductive elements in a first mold layer. A first redistribution layer (RDL) is placed over the first mold layer and electrically coupled with the first die. A second die is coupled with the first RDL, and the second die and first RDL are at least partially encapsulated in a second mold layer. A second RDL is formed over the second mold layer and is electrically coupled with the second die. A third mold layer at least partially encapsulates the second RDL. A portion of the substrate is removed to expose (and a solder mask is applied to) surfaces of the electrically conductive elements and of the first mold layer to form a stacked embedded package.Type: ApplicationFiled: June 2, 2017Publication date: February 1, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng LIN, Francis J. CARNEY, Yenting WEN, Chee Hiong CHEW, Azhar ARIPIN
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Publication number: 20180005936Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng LIN, Yenting WEN, George CHANG
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Patent number: 9679878Abstract: Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically conductive elements, and at least partially encapsulating the first die and electrically conductive elements in a first mold layer. A first redistribution layer (RDL) is placed over the first mold layer and electrically coupled with the first die. A second die is coupled with the first RDL, and the second die and first RDL are at least partially encapsulated in a second mold layer. A second RDL is formed over the second mold layer and is electrically coupled with the second die. A third mold layer at least partially encapsulates the second RDL. A portion of the substrate is removed to expose (and a solder mask is applied to) surfaces of the electrically conductive elements and of the first mold layer to form a stacked embedded package.Type: GrantFiled: July 27, 2016Date of Patent: June 13, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Francis J. Carney, Yenting Wen, Chee Hiong Chew, Azhar Aripin
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Patent number: 9373600Abstract: In one embodiment, an electronic package structure includes a substrate having one or more conductive plane layers formed therein. The substrate also includes a plurality of conductive pads on major surface configured to provide electrical interconnects to a next level of assembly. At least one conductive plane layer is configured to have cut-outs above the solder pads so that at least portions of the solder pad are not overlapped by the conductive plane layer.Type: GrantFiled: November 24, 2014Date of Patent: June 21, 2016Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Yenting Wen
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Publication number: 20150214173Abstract: In one embodiment, an electronic package structure includes a substrate having one or more conductive plane layers formed therein. The substrate also includes a plurality of conductive pads on major surface configured to provide electrical interconnects to a next level of assembly. At least one conductive plane layer is configured to have cut-outs above the solder pads so that at least portions of the solder pad are not overlapped by the conductive plane layer.Type: ApplicationFiled: November 24, 2014Publication date: July 30, 2015Inventor: Yenting Wen
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Patent number: 8999807Abstract: A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke.Type: GrantFiled: May 27, 2010Date of Patent: April 7, 2015Assignee: Semiconductor Components Industries, LLCInventors: Li Jiang, Ryan J. Hurley, Sudhama C. Shastri, Yenting Wen, Wang-Chang Albert Gu, Phillip Holland, Der Min Liou, Rong Liu, Wenjiang Zeng
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Patent number: 8582317Abstract: A semiconductor component and a method of manufacturing the semiconductor component that reduces parasitic elements. A semiconductor chip is coupled to a semiconductor chip receiving area of a support structure. The semiconductor chip has at least two power semiconductor devices. A drain contact of a first power semiconductor device is coupled to a source contact of a second power semiconductor device and the drain and source contacts of the first and second power semiconductor devices are joined to the semiconductor chip receiving area. Another semiconductor chip may be bonded to a second semiconductor chip receiving area of the support structure. An energy storage element may be coupled between the source contact of the first power semiconductor device and the drain contact of the second semiconductor device. A protective structure may be formed over the semiconductor chips and the energy storage element.Type: GrantFiled: May 26, 2010Date of Patent: November 12, 2013Assignee: Semiconductor Components Industries, LLCInventors: Yenting Wen, Kisun Lee, Michael Stapleton, Gary H. Loechelt