Abstract: A luggage board for a vehicle includes a core layer; a first layer covering a portion of the core layer; and a second layer covering a remaining portion of the core layer except for a region covered by the first layer. End portions of the first layer and the second layer disposed on a side surface of the core layer are bonded to each other.

Abstract: A computing resource management system using software modularization in a cluster computing environment in which computing devices are connected, including an application process running on each computing device and an algorithm processing process configured to run independently of the application process and perform task processing on the application process, the computing resource management system including: a task managing system configured to receive a task request message from an application process requiring a task from each computing device; a process managing system configured to confirm an algorithm processing process of computing devices connected to the cluster computing environment, and determine whether there is an algorithm processing process in an idle state to which the application process requested for a task will be assigned; and a performed managing system configured to confirm a result of an application process whose task is performed by the algorithm processing process.

Abstract: A line buffer and a method of providing data to a 3×3 line interpolation processor using the line buffer in an image processing system, such as a digital camera, includes a readable and writable single memory, a buffer register having a prior data area storing first line image data, which has been stored in a memory, in a unit of 2m bits, and having a present data area storing second image data, which is inputted from an image sensor in a unit of m bits, in a unit of the 2m bits, and a memory controller providing the memory with a chip enable signal, a write enable signal, and an address indicating locations of the first and second line image data stored in the buffer register, reading and writing the first and second line image data from and on the memory, and outputting the first and second line image data and a third line image data, which is inputted from the image sensor.

Abstract: A digital white balance device is simply implemented in a digital processing scheme by employing a grey world algorithm. In the device, a timing controller receives vertical and horizontal synchronization signals of an input image and produces a timing control signal. An RGB multiplier multiplies input RGB image data by RGB gains received from an RGB gain controller. A first YCbCr averaging unit converts input RGB image data to YCbCr image data, and obtains first YCbCr averages of this YCbCr image data. A second YCbCr averaging unit converts output RGB image data to YCbCr image data, and obtains second YCbCr averages of this YCbCr image data. According to the timing control signal, the RGB gain controller compares the second YCbCr averages with predetermined target YCbCr averages, respectively, and obtains RGB gains based on the first YCbCr averages, according to the compared result, and provides them to the RGB multiplier.

Abstract: An apparatus for and a method of simultaneously performing edge detection and enhancement without any additional memory storage include an image sensor sensing an image to output image data, a line buffer receiving the image data to output the image data, a register storing the image data transmitted from the line buffer, an interpolation unit performing an interpolation operation on the image data received from the register, an edge detection unit performing an edge detection operation on the image data received from the register to output an edge detection signal in parallel to the interpolation operation of the interpolation unit according to a selection signal representing a pattern of the image data stored in the register, and an edge enhancement unit enhancing an output of the interpolation unit according to the edge detection unit of the edge detection unit.

Abstract: An apparatus for and a method of simultaneously performing edge detection and enhancement without any additional memory storage include an image sensor sensing an image to output image data, a line buffer receiving the image data to output the image data, a register storing the image data transmitted from the line buffer, an interpolation unit performing an interpolation operation on the image data received from the register, an edge detection unit perform an edge detection operation on the image data received from the register to output an edge detection signal in parallel to the interpolation operation of the interpolation unit according to a selection signal representing a pattern of the image data stored in the register, and an edge enhancement unit enhancing an output of the interpolation unit according to the edge detection unit of the edge detection unit.

Abstract: A line buffer and a method of providing data to a 3×3 line interpolation processor using the line buffer in an image processing system, such as a digital camera, includes a readable and writable single memory, a buffer register having a prior data area storing first line image data, which has been stored in a memory, in a unit of 2m bits, and having a present data area storing second image data, which is inputted from an image sensor in a unit of m bits, in a unit of the 2m bits, and a memory controller providing the memory with a chip enable signal, a write enable signal, and an address indicating locations of the first and second line image data stored in the buffer register, reading and writing the first and second line image data from and on the memory, and outputting the first and second line image data and a third line image data, which is inputted from the image sensor.

Abstract: An interface apparatus of an image processing system includes an image sensor sensing an image, an image processor processing the sensed image to output image data, and a sensor interface coupled between the image sensor and the image processor. The sensor interface includes a sensor type register storing information about the image sensor, a micom storing the information in the sensor type register to control the image sensor, and a sensor signal processor receiving signals corresponding to the sensed image from the image sensor, converting the signals into modified signals, which the image processor processes to output the image data, according to the information stored in the sensor type register, and transmitting the modified signals to the image processor.

Abstract: Disclosed is a data process method in a high-capacity flash erasable and programmable read-only memory (EEPROM) card system mounted with at least one flash EEPROM and a controller connected to a host computer, having an interface for down/up loading arbitrary data into the flash EEPROM data regions to access the host computer, the method including: a first procedure for setting a designated number of block regions that divide the flash EEPROM data regions into a designated arbitrary size and for sub-dividing each block region to a designated number of mapping table regions; and a second procedure for providing the flash EEPROM data regions to access the host computer with the sub-divided mapping table region unit on the basis of a look-up-table in a volatile memory region inside of the controller.