Patents by Inventor Yeon-Sil Sohn

Yeon-Sil Sohn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150249093
    Abstract: Provided is a semiconductor device, including gate structures on a substrate, the gate structures extending parallel to a first direction and being spaced apart from each other by a separation trench interposed therebetween, each of the gate structures including insulating patterns stacked on the substrate and a gate electrode interposed therebetween; vertical pillars connected to the substrate through the gate structures; an insulating spacer in the separation trench covering a sidewall of each of the gate structures; and a diffusion barrier structure between the gate electrode and the insulating spacer.
    Type: Application
    Filed: December 18, 2014
    Publication date: September 3, 2015
    Inventors: Jeonggil LEE, Yeon-Sil SOHN, Woonghee SOHN, Kihyun YOON, Myoungbum LEE, Tai-Soo LIM, Yong Chae JUNG
  • Publication number: 20150243675
    Abstract: Provided are a semiconductor memory device and a fabricating method thereof. The device includes a stack including vertical channel structures that penetrate insulating patterns and gate electrodes that are alternately and repeatedly stacked on each other. Each of the gate electrodes includes first and second gate conductive layers. In a first region between an outer side of the stack and the vertical channel structures, the first gate conductive layer is adjacent to the vertical channel structures and includes a truncated end portion, the second gate conductive layer has a portion adjacent to the vertical channel structures and covered by a corresponding one of the first gate conductive layer and an opposite portion that is not covered with the first gate conductive layer. In a second region between the vertical channel structures, the first gate conductive layer may be extended to continuously cover surfaces of the second gate conductive layer.
    Type: Application
    Filed: January 19, 2015
    Publication date: August 27, 2015
    Inventors: Tai-Soo LIM, Jeonggil LEE, Yeon-Sil SOHN, Woonghee SOHN, Myoungbum LEE, Yong-Chae JUNG
  • Publication number: 20150126007
    Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about ?0.1×109 dyne/cm2 to about ?10×109 dyne/cm2 to the substrate.
    Type: Application
    Filed: January 9, 2015
    Publication date: May 7, 2015
    Inventors: Kyung-Tae Jang, Myoungbum Lee, Seungmok Shin, JinGyun Kim, Yeon-Sil Sohn, Seung-Yup Lee, Dae-Hun Choi
  • Publication number: 20120064682
    Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about ?0.1×109 dyne/cm2 to about ?10×109 dyne/cm2 to the substrate.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 15, 2012
    Inventors: Kyung-Tae Jang, Myoung Lee, Seungmok Shin, JinGyun Kim, Yeon-Sil Sohn, Seung-Yuo Lee, Dae-Hun Choi