Abstract: The present invention provides a method for controlling the critical dimension of a mask in dual damascene process. The method comprises providing a semiconductor structure which has a contact pattern thereon. A dielectric layer, such as a spin-on glass layer, is formed on the semiconductor structure and the contact pattern. Then a photoresist layer is formed on the dielectric layer. Next, the photoresist layer and the dielectric layer are etched to expose partial the semiconductor structure. Then the exposed semiconductor structure is removed followed by removing the total photoresist layer and the total dielectric layer.

Abstract: A method of gap filling is provided. A substrate comprising conductive structures thereon is provided. A gap is between the conductive structures. A conformal first dielectric layer is formed on the substrate and is used to protect the conductive structures and the substrate. An implanting process is performed with a high angle to implant impurities into the first dielectric layer. A second dielectric layer is formed on the implanted first dielectric layer to fully fill the gap.

Abstract: A method of improving gap filling of dielectric layer by implantation is disclosed. When a plurality of semiconductor structures are formed on a semiconductor substrate, there are gaps between portions of the semiconductor structure. First, a dielectric layer is formed over the surface of the semiconductor structure and then an implantation process is employed to implant ions as BF2+, B3+ and F− into first dielectric layer and more particularly into part of the first dielectric layer that corresponds to sidewall of semiconductor structure. Afterwards, rapid thermal process is employed to form SiOF molecules and B2O5 molecules on the first dielectric layer, and then a second dielectric layer is formed over the first dielectric layer. Because SiOF molecules improve step coverage of the second dielectric layer formation and B2O5 molecules enhance fluidity of second dielectric layer during formation of the second dielectric layer.

Abstract: An improved method of forming an inter-metal dielectric layer on a semiconductor substrate is described. A plurality of conductive lines is formed on the substrate wherein an gap is simultaneously formed between every two conductive lines to expose a part of the substrate. A conformal first dielectric layer is formed on the plurality of conductive lines and the exposed substrate. A spin-coating material layer is formed in the gap wherein the first dielectric layer on top of the plurality of conductive lines is exposed. A plasma treatment is performed on the exposed first dielectric layer. The remaining spin-coating material layer is removed until the first dielectric layer is exposed. A second dielectric layer is formed over the first dielectric layer.

Abstract: The present invention is used to modulate uniformity of deposited layer thickness, and especially is related to the layer that is formed by chemical vapor deposition. The proposed method of the invention comprises following essential steps: Place a wafer on a wafer carrier; move the wafer carrier under a shower head inside a reactor; adjust a tilted angle between the shower head and the wafer; perform a depositing process to form a deposited layer on the wafer; and move the wafer carrier away from the shower head.

Abstract: A method for forming wiring structures in integrated circuit devices is disclosed. The method, in one embodiment, firstly providing a substrate is carried out. Then an interlayer dielectric layer is formed over the substrate. Sequentially an etching stop layer is formed and wherein the etching stop layer is patterned. Thus formation of a dielectric layer over the etching stop is achieved. Also photoresist mask is formed and defined. Therefore an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etching stop layer therein. Consequentially removing the photoresist mask and then depositing a first conductive metal layer are all carried out. Again, photoresist mask is formed and defined. The next step is removing excess parts of the conductive metal. Sequentially the step is depositing a second conductive metal layer. Finally the surface of integrated circuit device is planarized herein.

Abstract: The present invention relates to a method of forming a gate spacer on the semiconductor wafer. Two dielectric layers are first formed on the surface of the semiconductor wafer, the first dielectric layer is an USG dielectric layer and the second dielectric layer is a SOG dielectric layer. The SOG dielectric layer is formed by a spincoating process to create a flat surface on the semiconductor wafer. Afterward, the plasma etching, wet etching and dry etching processes are sequentially performed to remove the SOG dielectric layer and USG dielectric layer. Finally, the spacer is formed on the side-wall of the gate.

Abstract: The present invention provides a method of forming a dual damascene structure on a semiconductor wafer. The semiconductor wafer comprises a substrate, and a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer and a photoresist layer sequentially formed on the substrate. A dry-etching process is performed first to vertically remove a specific portion of the second silicon oxide layer down to the silicon nitride layer so as to form a hole. Then the photoresist layer is removed and the portion of the silicon nitride layer positioned under the hole is removed using a phosphoric acid solution. A lithographic process is then performed to form a photoresist layer on the second silicon oxide layer, the photoresist layer comprising a line-shaped opening positioned above the hole with a width larger than the diameter of the hole. Then an etching process is performed along the line-shaped opening to vertically remove the second silicon oxide layer and the first silicon oxide layer.