Patents by Inventor Yeong Jyh Lii

Yeong Jyh Lii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050035459
    Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.
    Type: Application
    Filed: September 22, 2004
    Publication date: February 17, 2005
    Inventors: Kathleen Yu, Kirk Strozewski, Janos Farkas, Hector Sanchez, Yeong-Jyh Lii
  • Patent number: 6287951
    Abstract: A hardmask layer (34) is formed over insulating layers (26, 24, 22 and 20), and an antireflective layer (36) is formed overlying the hardmask layer (34). A resist layer (38) is formed overlying the antireflective layer (36), and an opening is formed in the resist layer to expose a surface portion of the antireflective layer (36). The exposed surface portion of the antireflective layer (36) and portions of the hardmask layer (34) are etched to expose a surface portion of the insulating layers (26, 24, 22 and 20), and a feature opening (61) is formed in the insulating layers (26, 24, 22 and 20). A conductive material (74) is deposited to fill the feature opening (61), and portions of the conductive material (74) lying outside the opening are removed.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: September 11, 2001
    Assignee: Motorola Inc.
    Inventors: Kevin D. Lucas, Christopher D. Pettinato, Wayne D. Clark, Stanley M. Filipiak, Yeong Jyh Lii