Patents by Inventor Yeong-kwan Kim

Yeong-kwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170107614
    Abstract: One or more silicon nitride layers are deposited onto a substrate by exposing the surface of the substrate to radicals to activate the surface of the substrate. A silicon-containing first precursor with a high sticking coefficient is injected onto the substrate. A second precursor including molecules each having at least two Si atoms is injected onto the substrate. The first precursor has a higher sticking coefficient than the second precursor. The substrate is treated with nitrogen radicals N* to form multiple layers of silicon nitride per radical exposure. This results in high-quality silicon nitride films with high deposition rate.
    Type: Application
    Filed: October 12, 2016
    Publication date: April 20, 2017
    Inventors: Sang In LEE, Yeong Kwan KIM, Jungyup KIM
  • Patent number: 7547952
    Abstract: The present invention generally is a method for forming a high-k dielectric layer, comprising depositing a hafnium compound by atomic layer deposition to a substrate, comprising, delivering a hafnium precursor to a surface of the substrate, reacting the hafnium precursor and forming a hafnium containing layer to the surface, delivering a nitrogen precursor to the hafnium containing layer, forming at least one hafnium nitrogen bond and depositing the hafnium compound to the surface.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: June 16, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Craig Metzner, Shreyas Kher, Yeong Kwan Kim, M. Noel Rocklein, Steven M. George
  • Patent number: 7544607
    Abstract: A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate stack patterns functioning as a gate line, a first bubble prevention layer formed on the gate spacers and the gate stack patterns, bit line spacers formed on the sidewalls of bit line stack patterns functioning as a bit line, and a second bubble prevention layer formed on the bit line spacers and the gate stack patterns and at least one of the above is formed of a multi-layer of a silicon nitride layer and a silicon oxide layer, or a multi-layer of a silicon oxide layer and a silicon nitride layer, thereby filling the trench, gate stack patterns, or bit line stack patterns without a void.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: June 9, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-kwan Kim, Dong-chan Kim, Seung-hwan Lee, Young-wook Park
  • Patent number: 7316954
    Abstract: The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1-xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided. Related methods of fabricating integrated circuit devices are also provided.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: January 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-jeong Oh, Yeong-kwan Kim, Seung-hwan Lee, Dong-chan Kim, Young-wook Park
  • Publication number: 20070210367
    Abstract: A storage capacitor includes a first electrode layer, second electrode layer and a dielectric interlayer arranged between the first electrode layer and the second electrode layer. The dielectric interlayer contains a high-k dielectric and at least one silicon-containing component.
    Type: Application
    Filed: November 30, 2006
    Publication date: September 13, 2007
    Applicant: QIMONDA AG
    Inventors: Henry Bernhardt, Thomas Hecht, Michael Stadtmueller, Christian Kapteyn, Uwe Schroder, Yeong-Kwan Kim, Andreas Spitzer
  • Patent number: 7052918
    Abstract: A multi-layer film for a thin film structure, a capacitor using the multi-layer film and methods for fabricating the multi-layer film and the capacitor, the multi-layer film including a composition transition layer between a lower material layer and an upper material layer respectively formed of different elements whose interaction parameters are different from each other, the composition transition layer containing both elements of the lower and upper material layers, the concentration of the composition transition layer gradually varying from the portion of the composition transition layer contacting with the lower material layer to the portion of the composition transition layer contacting with the upper material layer such that the concentration of the element of the upper material layer is relatively large in its portion adjacent to the upper material layer, each of the lower and upper material layers being formed of an oxide or nitride material of aluminum, silicon, zirconium, cerium, titanium, yttrium,
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: May 30, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-soon Lim, Yeong-kwan Kim, Heung-soo Park, Sang-in Lee
  • Publication number: 20050087828
    Abstract: A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate stack patterns functioning as a gate line, a first bubble prevention layer formed on the gate spacers and the gate stack patterns, bit line spacers formed on the sidewalls of bit line stack patterns functioning as a bit line, and a second bubble prevention layer formed on the bit line spacers and the gate stack patterns and at least one of the above is formed of a multi-layer of a silicon nitride layer and a silicon oxide layer, or a multi-layer of a silicon oxide layer and a silicon nitride layer, thereby filling the trench, gate stack patterns, or bit line stack patterns without a void.
    Type: Application
    Filed: November 18, 2004
    Publication date: April 28, 2005
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeong-kwan Kim, Dong-chan Kim, Seung-hwan Lee, Young-wook Park
  • Publication number: 20050064660
    Abstract: The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1-xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided. Related methods of fabricating integrated circuit devices are also provided.
    Type: Application
    Filed: October 19, 2004
    Publication date: March 24, 2005
    Inventors: Sang-jeong Oh, Yeong-kwan Kim, Seung-hwan Lee, Dong-chan Kim, Young-wook Park
  • Patent number: 6833310
    Abstract: A semiconductor device having a thin film formed by atomic layer deposition and a method for fabricating the same, wherein the semiconductor device includes a liner layer formed on an internal wall and bottom of a trench, gate spacers formed on the sidewalls of gate stack patterns functioning as a gate line, a first bubble prevention layer formed on the gate spacers and the gate stack patterns, bit line spacers formed on the sidewalls of bit line stack patterns functioning as a bit line, and a second bubble prevention layer formed on the bit line spacers and the gate stack patterns and at least one of the above is formed of a multi-layer of a silicon nitride layer and a silicon oxide layer, or a multi-layer of a silicon oxide layer and a silicon nitride layer, thereby filling the trench, gate stack patterns, or bit line stack patterns without a void.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: December 21, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-kwan Kim, Dong-chan Kim, Seung-hwan Lee, Young-wook Park
  • Patent number: 6828218
    Abstract: The present invention provides a method of forming a thin film using atomic layer deposition (ALD). An ALD reactor having a single reaction space is provided. A batch of substrates is concurrently loaded into the single reaction space of the ALD reactor. Then, a gas containing reactants is introduced into the single reaction space, and a portion of the reactants is chemisorbed on top surfaces of the batch of substrates within the single reaction space. Non-chemically adsorbed reactants are then removed from the single reaction space. In accordance with one embodiment of the present invention, after introducing the gas containing reactants, non-chemically adsorbed reactants are diluted in the single reaction space to facilitate the removal of non-chemically adsorbed reactants.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: December 7, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Kwan Kim, Young-Wook Park, Seung-Hwan Lee
  • Patent number: 6828616
    Abstract: The present invention provides an integrated circuit device that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1−xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: December 7, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-jeong Oh, Yeong-kwan Kim, Seung-hwan Lee, Dong-chan Kim, Young-wook Park
  • Publication number: 20040198069
    Abstract: The present invention generally is a method for forming a high-k dielectric layer, comprising depositing a hafnium compound by atomic layer deposition to a substrate, comprising, delivering a hafnium precursor to a surface of the substrate, reacting the hafnium precursor and forming a hafnium containing layer to the surface, delivering a nitrogen precursor to the hafnium containing layer, forming at least one hafnium nitrogen bond and depositing the hafnium compound to the surface.
    Type: Application
    Filed: April 4, 2003
    Publication date: October 7, 2004
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Craig Metzner, Shreyas Kher, Yeong Kwan Kim, M. Noel Rocklein, Steven M. George
  • Publication number: 20030207529
    Abstract: A multi-layer film for a thin film structure, a capacitor using the multi-layer film and methods for fabricating the multi-layer film and the capacitor, the multi-layer film including a composition transition layer between a lower material layer and an upper material layer respectively formed of different elements whose interaction parameters are different from each other, the composition transition layer containing both elements of the lower and upper material layers, the concentration of the composition transition layer gradually varying from the portion of the composition transition layer contacting with the lower material layer to the portion of the composition transition layer contacting with the upper material layer such that the concentration of the element of the upper material layer is relatively large in its portion adjacent to the upper material layer, each of the lower and upper material layers being formed of an oxide or nitride material of aluminum, silicon, zirconium, cerium, titanium, yttrium,
    Type: Application
    Filed: April 10, 2003
    Publication date: November 6, 2003
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Soon Lim, Yeong-Kwan Kim, Heung-Soo Park, Sang-In Lee
  • Patent number: 6576053
    Abstract: In a method of forming a thin film using an atomic layer deposition (ALD) method, a thin film is formed on a substrate in cycles. Each cycle includes injecting a first reactant including an atom that forms the thin film and a ligand into a reaction chamber that includes the substrate, purging the first reactant, injecting a second reactant into the reaction chamber, and purging the second reactant. The thin film is formed by a chemical reaction between the atom that forms the thin film and a second reactant whose binding energy with respect to the atom that forms the thin film is larger than the binding energy of the ligand with respect to the atom that forms the thin film and the generation of by-products is prevented. The generation of a hydroxide by-product in the thin film is suppressed by using a material that does not include a hydroxide as the second reactant, purging the second reactant, and reacting the second reactant with a third reactant that includes hydroxide.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: June 10, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-kwan Kim, Young-wook Park, Jae-soon Lim, Sung-je Choi, Sang-in Lee
  • Patent number: 6570253
    Abstract: A multi-layer film for a thin film structure, a capacitor using the multi-layer film and methods for fabricating the multi-layer film and the capacitor, the multi-layer film including a composition transition layer between a lower material layer and an upper material layer respectively formed of different elements whose interaction parameters are different from each other, the composition transition layer containing both elements of the lower and upper material layers, the concentration of the composition transition layer gradually varying from the portion of the composition transition layer contacting with the lower material layer to the portion of the composition transition layer contacting with the upper material layer such that the concentration of the element of the upper material layer is relatively large in its portion adjacent to the upper material layer, each of the lower and upper material layers being formed of an oxide or nitride material of aluminum, silicon, zirconium, cerium, titanium, yttrium,
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: May 27, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-soon Lim, Yeong-kwan Kim, Heung-soo Park, Sang-in Lee
  • Publication number: 20030066483
    Abstract: An atomic layer deposition apparatus and a method of operating the same are provided. The atomic layer deposition apparatus is used to deposit an atomic layer by repeatedly supplying and purging a process gas, and includes a chamber used for depositing an atomic layer, a gas injection hole through which the process gas is supplied to the chamber, a first outlet through which particles or remnants are removed from the chamber when supplying the process gas, and a second outlet through which exhaust gas is discharged from the chamber when purging the process gas.
    Type: Application
    Filed: September 25, 2002
    Publication date: April 10, 2003
    Applicant: Samsung Electronics Co., Inc.
    Inventors: Joo-Won Lee, Yeong-Kwan Kim, Jae-Eun Park
  • Patent number: 6509601
    Abstract: A semiconductor memory device having a capacitor protection layer and a method for manufacturing the same. A capacitor of the semiconductor memory device is entirely covered with an encapsulating layer having a multi-layered structure. The encapsulating layer comprises at least a blocking layer and a capacitor protection layer, each of which is formed of different materials. The blocking is formed of a material capable of preventing a capacitor dielectric layer from volatilizing and/or capable of preventing a reaction between a material layer under the blocking layer and the capacitor protection layer. The capacitor protection layer is formed of a material layer capable of preventing diffusion of hydrogen into the capacitor dielectric layer. In addition, the semiconductor memory device may has a hydrogen barrier layer as another capacitor protection layer, between the capacitor and a passivation layer.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: January 21, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-tak Lee, Hag-ju Cho, Yeong-kwan Kim
  • Publication number: 20030013320
    Abstract: The present invention provides a method of forming a thin film using atomic layer deposition (ALD). An ALD reactor having a single reaction space is provided. A batch of substrates is concurrently loaded into the single reaction space of the ALD reactor.
    Type: Application
    Filed: May 31, 2001
    Publication date: January 16, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Kwan Kim, Young-Wook Park, Seung-Hwan Lee
  • Publication number: 20030003230
    Abstract: A method for manufacturing a thin film includes the steps of loading a substrate into a reaction chamber, and terminating the surface of the substrate loaded into the reaction chamber by a specific atom. A first reactant is chemically adsorbed on the terminated substrate by injecting the first reactant into the reaction chamber including the terminated substrate. After removing the first reactant physically adsorbed into the terminated substrate, a solid thin film is formed through chemical exchange or reaction of the chemically adsorbed first reactant and a second reactant by injecting the second reactant into the reaction chamber. According to the thin film manufacturing method according to the present invention, it is possible to grow a thin film on the substrate in a state in which the no or little impurities and physical defects are generated in the thin film and interface of the thin film.
    Type: Application
    Filed: August 21, 2002
    Publication date: January 2, 2003
    Inventors: Yeong-kwan Kim, Sang-in Lee, Chang-soo Park, Sang-min Lee
  • Publication number: 20020195683
    Abstract: A semiconductor device includes a first electrode formed of a silicon-family material, a dielectric layer formed by sequentially supplying reactants on the first electrode, and a second electrode having a work function larger than that of the first electrode, with the second electrode being formed on the dielectric layer. The first electrode and the second electrode can be a lower electrode and an upper electrode, respectively, in a capacitor structure. Also, the first electrode and the second electrode can be a silicon substrate and a gate electrode, respectively, in a transistor structure. A stabilizing layer, which is, for example, a silicon oxide layer, a silicon nitride layer, or a composite layer of the silicon oxide layer and the silicon nitride layer, for facilitating the formation of the dielectric layer by hydrophilizing the surface of the first electrode, may be formed on the first electrode. The dielectric layer can be formed by an atomic layer deposition method.
    Type: Application
    Filed: March 27, 2000
    Publication date: December 26, 2002
    Inventors: Yeong-kwan Kim, Heung-soo Park, Young-wook Park, Sang-in Lee, Yoon-hee Chang, Jong-ho Lee, Sung-je Choi, Seung-hwan Lee, Jae-soon Lim, Joo-won Lee