Patents by Inventor Yeong Seok Kim
Yeong Seok Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240154530Abstract: The present disclosure relates to a power circuit and a display device including the same. The power circuit includes an output terminal configured to supply an output voltage to a digital circuit; a current sensing resistor connected to the output terminal; a sensing part configured to receive a first reference voltage and voltages of both ends of the current sensing resistor and vary one of a feedback voltage and a second reference voltage; and a voltage generation part configured to receive the feedback voltage and the second reference voltage and lowers the output voltage when a current flowing through the current sensing resistor decreases.Type: ApplicationFiled: October 2, 2023Publication date: May 9, 2024Applicant: LG Display Co., Ltd.Inventors: Bong Hwan KIM, Yeong Seok CHOE
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Publication number: 20240122025Abstract: A display device includes: a pixel defining layer defining openings arranged in first and second directions, the openings forming emission areas in which light emitting elements are disposed to emit light of different colors; a light blocking layer disposed on the pixel defining layer, and defining holes, each overlapping the opening and having a larger diameter than the opening; and color filters disposed on the light blocking layer to overlap the holes and overlap the emission areas. The opening has an opening interval, which is defined as a difference in diameter between the overlapping hole and the opening, in the openings, among homogeneous openings in which the light emitting elements for emitting light of the same color are disposed, the homogeneous openings adjacent in the first or second direction have different opening intervals, and among the homogeneous openings, openings having different opening intervals are at least three types.Type: ApplicationFiled: May 2, 2023Publication date: April 11, 2024Inventors: Chan Young KIM, Yeong Ho LEE, Ha Seok JEON, Jun Hee LEE, Choong Youl IM, Hyun Duck CHO, Kook Hyun CHOI
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Publication number: 20240111199Abstract: The lighting device disclosed in the embodiment includes a substrate, a light emitting device disposed on a lower surface of the substrate, a reflective layer disposed to face a light emitting surface of the light emitting device, a first resin layer disposed between the substrate and the reflective layer, and a light-transmission control layer disposed on an upper surface of the substrate, wherein the light-transmission control layer may include a liquid crystal layer including a cholesteric liquid crystal, and light emitted through the light emitting surface of the light emitting device may be reflected by the reflective layer and be provided to the light-transmission control layer through the substrate.Type: ApplicationFiled: December 14, 2023Publication date: April 4, 2024Inventors: Yeong Seok YU, Do Yub KIM, Se Yeon CHOI
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Publication number: 20240087439Abstract: The present disclosure relates to a system for safety management based on a cascade deep learning network, and the system for safety management based on the cascade deep learning network includes a camera module that captures image of an area to be monitored at an industrial site; and a processor that receives and analyzes image data captured by the camera module in real time.Type: ApplicationFiled: July 26, 2023Publication date: March 14, 2024Applicant: HYUNDAI MOBIS CO., LTD.Inventors: Joon Hyung PARK, Hye Rin KIM, Yeong Seok KIM
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Patent number: 11513151Abstract: A test handler includes a pusher which includes a pusher end which comes into contact with a DUT (Device Under Test) to transfer heat, and a pusher body which conducts heat to the pusher end, the pusher end separating a test tray for fixing the DUT and the pusher body from each other; a porous match plate including a pusher arrangement region in which the pusher body is placed, and a plurality of holes placed adjacent to the pusher arrangement region; a heater placed on an upper surface of the porous match plate to control temperature of the pusher; and an airflow input port placed on the heater to provide the airflow to the plurality of holes, in which the airflow passes through the plurality of holes and passes through a separated space between the test tray and the pusher body.Type: GrantFiled: March 24, 2021Date of Patent: November 29, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Yeong Seok Kim, Suk Byung Chae, Dong Soo Lee, Sang Ho Jang
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Publication number: 20220026485Abstract: A test handler includes a pusher which includes a pusher end which comes into contact with a DUT (Device Under Test) to transfer heat, and a pusher body which conducts heat to the pusher end, the pusher end separating a test tray for fixing the DUT and the pusher body from each other; a porous match plate including a pusher arrangement region in which the pusher body is placed, and a plurality of holes placed adjacent to the pusher arrangement region; a heater placed on an upper surface of the porous match plate to control temperature of the pusher; and an airflow input port placed on the heater to provide the airflow to the plurality of holes, in which the airflow passes through the plurality of holes and passes through a separated space between the test tray and the pusher body.Type: ApplicationFiled: March 24, 2021Publication date: January 27, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Yeong Seok KIM, Suk Byung CHAE, Dong Soo LEE, Sang Ho JANG
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Patent number: 11205637Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.Type: GrantFiled: September 2, 2020Date of Patent: December 21, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Won-keun Kim, Kyung-suk Oh, Ji-han Ko, Kil-soo Kim, Yeong-seok Kim, Joung-phil Lee, Hwa-il Jin, Su-jung Hyung
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Patent number: 11171128Abstract: The semiconductor package including a first semiconductor package including a first semiconductor package substrate, and a first semiconductor chip on the first semiconductor package substrate, an interposer disposed on the first semiconductor package is provided. Interposer electrically connects the first semiconductor package with an external semiconductor package, and has first and second sides opposed to each other. The second side is located between the first side and the first semiconductor package substrate, a first recess is formed in the second side of the interposer. The first recess has side walls extended from the second side toward the first side of the interposer and an upper surface connected to the side walls and the upper surface of the first recess faces the first semiconductor chip and a via in the interposer. The via does not transmit an electrical signal between the first semiconductor package and the external semiconductor package.Type: GrantFiled: March 24, 2020Date of Patent: November 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun Hyeok Im, Hee Seok Lee, Tae Woo Kang, Yeong Seok Kim, Kyoung-Min Lee
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Patent number: 10879225Abstract: A semiconductor package includes a package substrate, a first semiconductor device arranged on the package substrate, at least one second semiconductor device on the first semiconductor device to partially cover the first semiconductor device from a top down view, a heat dissipating insulation layer coated on the first semiconductor device and the at least one second semiconductor device, a conductive heat dissipation structure arranged on the heat dissipating insulation layer on a portion of the first semiconductor device not covered by the second semiconductor device, and a molding layer on the package substrate to cover the first semiconductor device and the at least one second semiconductor device. The heat dissipating insulation layer is formed of an electrically insulating and thermally conductive material, and the conductive heat dissipation structure formed of an electrically and thermally conductive material.Type: GrantFiled: June 4, 2019Date of Patent: December 29, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won-Keun Kim, Kyung-Suk Oh, Hwa-Il Jin, Dong-Kwan Kim, Yeong-Seok Kim, Jae-Choon Kim, Seung-Tae Hwang
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Publication number: 20200402952Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.Type: ApplicationFiled: September 2, 2020Publication date: December 24, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Won-keun KIM, Kyung-suk OH, Ji-han KO, Kil-soo KIM, Yeong-seok KIM, Joung-phil LEE, Hwa-il JIN, Su-jung HYUNG
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Patent number: 10825795Abstract: A method of manufacturing a semiconductor device may include forming an adhesive film on a surface of a semiconductor chip, mounting the semiconductor chip on a substrate such that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip and the substrate curing the adhesive film by simultaneously performing a thermo-compression process and an ultraviolet irradiation process on the adhesive film disposed between the substrate and the semiconductor chip.Type: GrantFiled: May 30, 2019Date of Patent: November 3, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Yeong-Seok Kim
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Patent number: 10797021Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.Type: GrantFiled: April 12, 2019Date of Patent: October 6, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Won-keun Kim, Kyung-suk Oh, Ji-han Ko, Kil-soo Kim, Yeong-seok Kim, Joung-phil Lee, Hwa-il Jin, Su-jung Hyung
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Publication number: 20200219860Abstract: The semiconductor package including a first semiconductor package including a first semiconductor package substrate, and a first semiconductor chip on the first semiconductor package substrate, an interposer disposed on the first semiconductor package is provided. Interposer electrically connects the first semiconductor package with an external semiconductor package, and has first and second sides opposed to each other. The second side is located between the first side and the first semiconductor package substrate, a first recess is formed in the second side of the interposer. The first recess has side walls extended from the second side toward the first side of the interposer and an upper surface connected to the side walls and the upper surface of the first recess faces the first semiconductor chip and a via in the interposer. The via does not transmit an electrical signal between the first semiconductor package and the external semiconductor package.Type: ApplicationFiled: March 24, 2020Publication date: July 9, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun Hyeok Im, Hee Seok Lee, Tae Woo Kang, Yeong Seok Kim, Kyoung-Min Lee
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Publication number: 20200144222Abstract: A method of manufacturing a semiconductor device may include forming an adhesive film on a surface of a semiconductor chip, mounting the semiconductor chip on a substrate such that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip and the substrate curing the adhesive film by simultaneously performing a thermo-compression process and an ultraviolet irradiation process on the adhesive film disposed between the substrate and the semiconductor chip.Type: ApplicationFiled: May 30, 2019Publication date: May 7, 2020Inventor: Yeong-Seok KIM
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Publication number: 20200135710Abstract: A semiconductor package includes a package substrate, a first semiconductor device arranged on the package substrate, at least one second semiconductor device on the first semiconductor device to partially cover the first semiconductor device from a top down view, a heat dissipating insulation layer coated on the first semiconductor device and the at least one second semiconductor device, a conductive heat dissipation structure arranged on the heat dissipating insulation layer on a portion of the first semiconductor device not covered by the second semiconductor device, and a molding layer on the package substrate to cover the first semiconductor device and the at least one second semiconductor device. The heat dissipating insulation layer is formed of an electrically insulating and thermally conductive material, and the conductive heat dissipation structure formed of an electrically and thermally conductive material.Type: ApplicationFiled: June 4, 2019Publication date: April 30, 2020Inventors: Won-Keun KIM, Kyung-Suk OH, Hwa-Il JIN, Dong-Kwan KIM, Yeong-Seok KIM, Jae-Choon KIM, Seung-Tae HWANG
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Patent number: 10607971Abstract: The semiconductor package including a first semiconductor package including a first semiconductor package substrate, and a first semiconductor chip on the first semiconductor package substrate, an interposer disposed on the first semiconductor package is provided. Interposer electrically connects the first semiconductor package with an external semiconductor package, and has first and second sides opposed to each other. The second side is located between the first side and the first semiconductor package substrate, a first recess is formed in the second side of the interposer. The first recess has side walls extended from the second side toward the first side of the interposer and an upper surface connected to the side walls and the upper surface of the first recess faces the first semiconductor chip and a via in the interposer. The via does not transmit an electrical signal between the first semiconductor package and the external semiconductor package.Type: GrantFiled: May 1, 2018Date of Patent: March 31, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun Hyeok Im, Hee Seok Lee, Tae Woo Kang, Yeong Seok Kim, Kyoung-Min Lee
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Publication number: 20200075545Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.Type: ApplicationFiled: April 12, 2019Publication date: March 5, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Won-keun KIM, Kyung-suk Oh, Ji-han Ko, Kil-soo Kim, Yeong-seok Kim, Joung-phil Lee, Hwa-il Jin, Su-jung Hyung
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Publication number: 20190115325Abstract: The semiconductor package including a first semiconductor package including a first semiconductor package substrate, and a first semiconductor chip on the first semiconductor package substrate, an interposer disposed on the first semiconductor package is provided. Interposer electrically connects the first semiconductor package with an external semiconductor package, and has first and second sides opposed to each other. The second side is located between the first side and the first semiconductor package substrate, a first recess is formed in the second side of the interposer. The first recess has side walls extended from the second side toward the first side of the interposer and an upper surface connected to the side walls and the upper surface of the first recess faces the first semiconductor chip and a via in the interposer. The via does not transmit an electrical signal between the first semiconductor package and the external semiconductor package.Type: ApplicationFiled: May 1, 2018Publication date: April 18, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun Hyeok IM, Hee Seok LEE, Tae Woo KANG, Yeong Seok KIM, Kyoung-Min LEE
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Publication number: 20190051611Abstract: A semiconductor package includes a substrate, semiconductor chips disposed on the substrate, and a ground pad disposed on or in the substrate and adjacent to any one or any combination of the semiconductor chips. The semiconductor package further includes an encapsulant disposed to seal an upper portion of the substrate, the semiconductor chips, and the ground pad, a trench disposed through the encapsulant to the ground pad, to isolate the semiconductor chips, and an electromagnetic interference (EMI) shielding film disposed to cover a surface of the encapsulant and the trench, the EMI shielding film including an adhesive resin, and the EMI shielding film being electrically connected to the ground pad.Type: ApplicationFiled: January 10, 2018Publication date: February 14, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: YEONG SEOK KIM
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Patent number: 9845456Abstract: A composition for deriving the maturation of dendritic cells includes complex cytokines generated by the simulation, the expression of which is induced on EBV-infected B cells. The dendritic cell maturation process, which conventionally takes approximately 7 days, can be shortened to 2 days, thereby producing dendritic cells in a more economically advantageous and effective manner.Type: GrantFiled: March 20, 2014Date of Patent: December 19, 2017Assignee: INJE UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATIONInventors: Dae Young Hur, Ga Bin Park, Yeong Seok Kim, Hyun Kyung Lee, Dae Jin Kim