Abstract: A flash memory device, and a manufacturing method thereof, having advantages of protecting sidewalls of a floating gate and a control gate and preventing a recess of an active area of a source region are provided. The method includes forming a tunneling oxide layer on an active region of a semiconductor substrate, forming a floating gate, a gate insulation layer, and a control gate on the tunneling oxide layer, forming insulation sidewall spacers on sides of the floating gate and the control gate, and removing at least portions of the tunneling oxide layer and the device isolation layer so as to expose the active region.

Abstract: A method of forming a pad and a fuse in a semiconductor device. A copper layer located in both a fuse region and a pad region is formed in a dielectric layer. A first insulating layer is formed on the dielectric layer to cover the copper layer and selectively etched to expose the copper layer in the fuse region. An aluminum fuse is formed on the first insulating layer in the fuse region and connected to the exposed copper layer. A second insulating layer is formed on both the aluminum fuse and the first insulating layer and selectively etched together with the first insulating layer to expose the underlying copper layer in the pad region. An aluminum pad is formed on the second insulating layer in the pad region and connected to the exposed copper layer in the pad region. At least one third insulating layer is formed on both the aluminum pad and the second insulating layer and selectively etched to expose the aluminum pad only.

Abstract: Provided is a CMOS (complementary metal oxide semiconductor) image sensor and a manufacturing method thereof. In the method, a photodiode, an interlayer insulating layer, a color filter layer, and a planarizing layer are sequentially formed on a substrate. A photoresist is applied on the planarizing layer. The photoresist is selectively patterned to form a plurality of photoresist patterns. A surface of each photoresist is hardened. The hardened photoresist patterns are reflowed to form microlenses.

Abstract: Methods of fabricating a semiconductor device are provided. A photoresist pattern can be formed on an implantation target layer, and conductive impurities can be implanted into the implantation target layer using the photoresist pattern as a mask. A portion of the photoresist pattern can be removed, conductive impurities implanted in the photoresist pattern can be cleaned, and the remaining portion of the photoresist pattern can be removed.

Abstract: A flash memory device, and a manufacturing method thereof, having advantages of protecting sidewalls of a floating gate and a control gate and preventing a recess of an active area of a source region are provided. The method includes forming a tunneling oxide layer on an active region of a semiconductor substrate, forming a floating gate, a gate insulation layer, and a control gate on the tunneling oxide layer, forming insulation sidewall spacers on sides of the floating gate and the control gate, and removing at least portions of the tunneling oxide layer and the device isolation layer so as to expose the active region.

Abstract: A flash memory device, and a manufacturing method thereof, having advantages of protecting sidewalls of a floating gate and a control gate and preventing a recess of an active area of a source region are provided. The method includes forming a tunneling oxide layer on an active region of a semiconductor substrate, forming a floating gate, a gate insulation layer, and a control gate on the tunneling oxide layer, forming insulation sidewall spacers on sides of the floating gate and the control gate, and removing at least portions of the tunneling oxide layer and the device isolation layer so as to expose the active region.

Abstract: Provided is a semiconductor device capable of reducing the resistance of the gate electrode of a transistor. The semiconductor device comprises a semiconductor substrate, a gate oxide film formed on the substrate, a gate formed on the gate oxide film, and a metal silicide layer formed on the top surface and the upper side surface of the gate.

Abstract: Provided is a method of fabricating a CMOS image sensor. According to an embodiment method, an insulating layer can be formed on a semiconductor substrate, and a metal pad can be formed on the insulating layer. A first overcoat layer can be formed on the insulating layer including the metal pad. The first overcoat layer can be selectively removed to expose a portion of the metal pad. A protective layer can be formed on the exposed metal pad and the first overcoat layer. A color filter array can be formed on the protective layer, and a second overcoat layer can be formed on the color filter array and the protective layer. The second overcoat layer can be selectively removed to remain on a photodiode region. A plasma treatment can then be performed on the remaining second overcoat layer before forming a microlens.

Abstract: A method of fabricating a CMOS image sensor is disclosed that enhances device robustness. The method includes the steps of forming a metal pad on a pad area of a substrate, forming a planarizing layer on the substrate including the metal pad, removing a portion of the planarizing layer to open a surface of the metal pad, forming a protective layer over the substrate including the metal pad, coating a color filter resist layer on the protective layer and selectively exposing the color filter resist layer, coating a microlens resist layer on the color filter resist layer and selectively exposing the microlens resist layer, developing the exposed color filter and microlens resist layers, forming a pad opening by selectively removing the protective layer to open a surface of the metal, and reflowing the microlens pattern.

Abstract: A method of fabricating a CMOS image sensor is disclosed that enhances device robustness. The method includes the steps of forming a metal pad on a pad area of a substrate, forming a planarizing layer on the substrate including the metal pad, removing a portion of the planarizing layer to open a surface of the metal pad, forming a protective layer over the substrate including the metal pad, coating a color filter resist layer on the protective layer and selectively exposing the color filter resist layer, coating a microlens resist layer on the color filter resist layer and selectively exposing the microlens resist layer, developing the exposed color filter and microlens resist layers, forming a pad opening by selectively removing the protective layer to open a surface of the metal, and reflowing the microlens pattern.

Abstract: A method of forming a gate electrode of a semiconductor device includes forming a damascene pattern for fabricating a metal electrode on an upper part of a poly silicon gate so as to prevent a metal electrode from being oxidized when the poly silicon electrode and the metal electrode are formed simultaneously. The method of forming the gate electrode of the semiconductor device includes the steps of forming a gate including poly silicon with a plurality of layers at an upper part of a silicon substrate, forming a spacer on a sidewall of the gate, vapor depositing inter layer dielectric between gates at the upper part of the substrate, forming a damascene pattern to which a metal electrode is formed, and completing the gate electrode including poly silicon and metal by filling the damascene pattern with a predetermined metal and planarizing the metal.

Abstract: Provided is a method of fabricating a CMOS image sensor. According to an embodiment method, an insulating layer can be formed on a semiconductor substrate, and a metal pad can be formed on the insulating layer. A first overcoat layer can be formed on the insulating layer including the metal pad. The first overcoat layer can be selectively removed to expose a portion of the metal pad. A protective layer can be formed on the exposed metal pad and the first overcoat layer. A color filter array can be formed on the protective layer, and a second overcoat layer can be formed on the color filter array and the protective layer. The second overcoat layer can be selectively removed to remain on a photodiode region. A plasma treatment can then be performed on the remaining second overcoat layer before forming a microlens.

Abstract: A flash memory device, and a manufacturing method thereof, having advantages of protecting sidewalls of a floating gate and a control gate and preventing a recess of an active area of a source region are provided. The method includes forming a tunneling oxide layer on an active region of a semiconductor substrate, forming a floating gate, a gate insulation layer, and a control gate on the tunneling oxide layer, forming insulation sidewall spacers on sides of the floating gate and the control gate, and removing at least portions of the tunneling oxide layer and the device isolation layer so as to expose the active region.

Abstract: A patterning layer of a single or multiple layer structure formed on a lower layer may be etched to form one or more steps therein, when the patterning layer is first dry etched to a partial depth thereof using a first resist pattern and then the patterning layer is etched again using a second resist pattern formed by lateral etching of the first resist pattern.

Abstract: Methods for fabricating a semiconductor device with salicide are disclosed. One example method includes forming a gate electrode structure having a gate oxide film, a gate electrode, and a protection film stacked on a substrate in succession, and gate spacers on sidewalls of the stack of the gate oxide film, the gate electrode, and the protection film; forming an insulating film on an entire surface of the substrate, the insulating film exposing upper portions of the gate electrode and the gate spacers; and removing portions of the protection film and the gate spacers, to expose an upper portion of the gate electrode. The example method may also include applying a salicide forming metal on an entire surface of the substrate; and performing a heat treatment process to form salicide on the gate electrode and the gate spacers, selectively.