Patents by Inventor Yeow Chon Ong

Yeow Chon Ong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145457
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a controller, a first mold compound surrounding the controller, a plurality of semiconductor dies, a second mold compound surrounding the plurality of semiconductor dies, and one or more through-mold interconnects electrically coupling the controller to the plurality of semiconductor dies.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 2, 2024
    Inventors: Faxing CHE, Yeow Chon ONG, Wei YU, Ling PAN
  • Publication number: 20240063141
    Abstract: A semiconductor package can include a substrate having bonded thereto an array of solder joints. Each of the solder joints in the array can have a first surface area and a first shape. The semiconductor package can further include at least one differently-sized solder joint having a second surface area larger than the first surface area. The differently-sized solder joint can have a second shape different from the first shape. Other systems, methods and apparatuses are described.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Inventors: Faxing Che, Yeow Chon Ong
  • Publication number: 20240063165
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, an adhesive assembly configured for semiconductor die attachment includes one or more adhesive films capable of semiconductor die attachment, and one or more conductive elements embedded in the one or more adhesive films.
    Type: Application
    Filed: August 18, 2022
    Publication date: February 22, 2024
    Inventors: Ramesh NALLAVELLI, Nagavenkata Varaprasad NUNE, Yeow Chon ONG, Hong Wan NG
  • Publication number: 20240047285
    Abstract: A semiconductor device assembly includes a semiconductor die, a substrate, and a spacer directly coupled to the substrate. The spacer includes a flexible main body and a support structure embedded in the flexible main body, wherein the support structure has a higher stiffness than the flexible main body. The spacer carries the semiconductor die. The flexible main body of the spacer mitigates the effects of thermomechanical stress, for example caused by a mismatch between the coefficient of thermal expansion of the semiconductor die and the substrate. The embedded support structure provides strength needed to support the semiconductor die during assembly.
    Type: Application
    Filed: August 8, 2022
    Publication date: February 8, 2024
    Inventors: Faxing Che, Wei Yu, Yeow Chon Ong, Shin Yueh Yang, Hong Wan Ng
  • Publication number: 20240038704
    Abstract: In some embodiments, a semiconductor device assembly can include a first semiconductor die, a second semiconductor die, and an interconnection structure therebetween. The interconnection structure can directly electrically couple the first and the second semiconductor dies. The interconnection structure can include an inner metallic pillar, an outer metallic shell, a continuous metallic bridging layer, and a dielectric liner. The outer metallic shell can surround and be spaced from the inner metallic pillar, the continuous metallic bridging layer can be over and connected with the inner metallic pillar and the outer metallic shell, and the dielectric liner can be between the inner metallic pillar and the outer metallic shell. In some embodiments, the second semiconductor die can be excluded and the interconnection structure can solely be coupled to the first semiconductor die.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 1, 2024
    Inventors: Faxing Che, Hong Wan Ng, Yeow Chon Ong
  • Publication number: 20230207488
    Abstract: A semiconductor package assembly includes a substrate, a die stack including at least a bottom die, an inert top spacer, and at least a first inert base spacer. The inert top and base spacers are exclusive of any circuits. A top surface of the inert top spacer is directly attached to a bottom surface of the bottom die in the die stack. A top surface of the first inert base spacer is directly attached to a bottom surface of the inert top spacer and a bottom surface of the first inert base spacer is directly attached to the substrate. The footprint of the inert base spacer is smaller than the footprint of the inert top spacer. In some embodiments, the footprint of the inert base spacer is positioned entirely within the footprint of the inert top spacer.
    Type: Application
    Filed: October 28, 2022
    Publication date: June 29, 2023
    Inventors: Faxing Che, Hong Wan Ng, Yeow Chon Ong, Wei Yu, Ling Pan, Lin Bu
  • Publication number: 20220208632
    Abstract: Systems and methods for a semiconductor device having reinforced packaging are provided. The device generally includes a substrate and one or more integrated circuit dies electrically coupled to the substrate with wire bonds. The device includes an encapsulant enclosing the one or more dies and the wire bonds. The package can include a reinforcing layer positioned on one or more surfaces of the encapsulant, a reinforcing wire extending through the encapsulant, or entrained reinforcing fiber portions positioned throughout the encapsulant. The reinforcing layer can be textile woven from synthetic or natural fibers, such as aramid, carbon, or glass. The package can be formed by disposing a reinforcing textile layer in a mold, placing a die and substrate in the mold with a liquid encapsulant, and hardening the liquid encapsulant to adhere the reinforcing textile layer, the encapsulant, the die, and the substrate together.
    Type: Application
    Filed: December 15, 2021
    Publication date: June 30, 2022
    Inventors: Suresh K. Upadhyayula, Yeow Chon Ong, Hong Wan Ng