Abstract: A 24-transistor D flip-flop circuit operates in a sampling mode when a clock signal has a first voltage state, and a holding mode when the clock signal has a second voltage state. The flip-flop circuit includes an internal control node coupled to a reference voltage node by way of a transistor controllable to couple the internal control node to the reference voltage node when the clock signal has the second voltage state. The flip-flop has very low power dissipation as it includes a 4-transistor change-sense component to detect changes in input data. The change-sense component is coupled in series with the transistor and receives an indication of an input voltage state of the flip-flop circuit and an indication of an output voltage state of the flip-flop circuit, and inhibits toggling of the internal control node if the indicated input voltage state and the indicated output voltage state are the same.

Abstract: A host controller is suitable for transferring data in transactions, each transaction being described by a transfer descriptor, and the transactions include split transactions. The transfer descriptor for a split transaction includes a bit which may be set to indicate whether the split transaction is a start split or a complete split transaction, and, once a transaction comprising split transactions has been started by a first split transaction, subsequent split transactions are generated automatically until the transaction is complete.

Abstract: An electronic device, operating as a USB host, has an embedded processor and a system memory, connected by a memory bus. A host controller integrated circuit does not need to master the system memory, but instead acts purely as a slave. The embedded processor is then adapted to write the data to the host controller integrated circuit in the form of transfer-based transactions.

Abstract: A bus station in the form of a hardware dongle, operates in conjunction with a USB Device running suitable software. When the bus station determines that a bus host is connected to a first bus communication port thereof, it acts as a transceiver to allow conventional bus communications between said bus host and a bus device connected to a second bus communication port thereof. When the bus station determines that a bus device running suitable software is connected to the first bus communication port thereof, it acts as an alternate host to allow bus communications between said bus device connected to the first bus communication port and a bus device connected to a second bus communication port.

Abstract: A method of transferring bulk and control data from a first device to a second device over a USB bus comprises storing transfer descriptors, each including a transfer descriptor header and payload data, in a buffer memory in the first device. The data is read in packets for transfer to the second device, with packets being read from the transfer descriptors cyclically. When the first and second transfer descriptor headers, in first and second transfer descriptors respectively, define a common endpoint, data packets are read from only the first transfer descriptor, until such time as it is detected that all data packets from the first transfer descriptor have been transmitted, and thereafter data packets are read from the second transfer descriptor.

Abstract: The invention relates to a bus system comprising a first station and a second station coupled by a bus for transferring data and control signals. The bus is conceived to operate according to a protocol in which the first station repeatedly sends requests to the second station. The first station comprises a processor, a bus interface, and a buffer coupled to said interruptible processor and said bus interface, the processor being operable to generate request properties for the requests to be sent by the first station. Furthermore, the processor is operable to handle said data items. The buffer is operable to store said request properties. The bus interface is operable to generate said requests from said stored request properties and to repeatedly send said requests.

Abstract: The invention relates to a bus system comprising a first station and a second station coupled by a bus for transferring data and control signals. The bus is conceived to operate according to a protocol in which the first station repeatedly sends requests to said second station and the second station responds to the requests. The first station comprises an interruptible processor and a bus interface. The bus interface is operable to interrupt the interruptible processor upon reception of selected responses of the second station. The interruptible processor is operable to handle the interrupts of the bus interface.

Abstract: The invention relates to a bus system comprising a first station (202) and a second station (203), (204), coupled by a bus for transferring messages, said bus being designed to operate in accordance with a protocol in which said first station (202) periodically sends messages in a predetermined order to the second station (203), (204), wherein said first station (202) comprises an interruptible processor (206), a memory element (208) comprising a buffer (501, 502), and a bus interface (207), wherein said interruptible processor (206) can be operated so as to generate a plurality of series of message properties; wherein said processor (206) can further be operated so as to issue a first series of message properties from among said plurality of series of message properties to said buffer (501, 503), and upon receipt of an interrupt signal from said bus interface issues a second series of message properties from among said plurality of series of message properties; wherein said buffer (501, 502) has a storage

Abstract: The invention relates to a bus system comprising a first station (202) and a second station (203, 204) coupled by a bus for transferring data and control signals. The bus is conceived to operate according to a protocol in which the first station (202) repeatedly sends requests to the second station (203, 204). The first station (202) comprises a processor (206), a bus interface (207), and a buffer (208) coupled to said interruptible processor and said bus interface, the processor (206) being operable to generate request properties for the requests to be sent by the first station (202). Furthermore, the processor (206) is operable to handle said data items. The buffer (208) is operable to store said request properties. The bus interface (207) is operable to generate said requests from said stored request properties and to repeatedly send said requests.

Abstract: The invention relates to a bus system comprising a first station (202) and a second station (203, 204) coupled by a bus for transferring data and control signals. The bus is conceived to operate according to a protocol in which the first station (202) repeatedly sends requests to said second station (203, 204) and the second station responds to the requests. The first station (202) comprises an interruptible processor (206) and a bus interface (207). The bus interface (207) is operable to interrupt the interruptible processor (206) upon reception of selected responses of the second station (203, 204). The interruptible processor (206) is operable to handle the interrupts of the bus interface (207).

Abstract: The invention relates to a bus system comprising a first station (202) and a second station (203), (204), coupled by a bus for transferring messages, said bus being designed to operate in accordance with a protocol in which said first station (202) periodically sends messages in a predetermined order to the second station (203), (204), wherein