Abstract: A method and system for predictive emergency notification of a vehicle passing through a dark coverage area (DCA). The method comprises continuously monitoring at least speed and position of the vehicle; monitoring available cellular tower signal strength indicators to predict entrance into a DCA; comparing said position of the vehicle with information about boundaries of DCAs to determine whether the vehicle is about to enter the DCA; calculating a lapsed time for the vehicle to emerge from the DCA, wherein the lapsed time calculated using at least one of an entry point to the DCA, an exit point from the DCA, and an average speed of the vehicle; tracking the vehicle and the lapsed time to ensure that the vehicle is out of the DCA within the lapsed time; and notifying of a possible emergency if the vehicle has not emerged from the DCA within the lapsed time.

Abstract: One embodiment of an apparatus for receiving a GPS signal includes a first chamber having a GPS antenna that is positionable relative to a second chamber having a GPS receiver, a communication path extending between the first and second chambers for connecting the GPS antenna and the GPS receiver, and a lock for fixing the relative movement of the first and second chambers, wherein the first chamber is positioned relative to the second chamber for optimum reception of the GPS signal by the GPS antenna. A system including such apparatus and method of using are also disclosed.

Abstract: An apparatus for collecting, storing and transmitting vehicle information. The apparatus comprises an on-board diagnostic (OBD) port interface for providing connection to an OBD port of a vehicle; a plurality of engine sensory monitors for collecting at least engine status and diagnostic information; a plurality of non-engine sensory monitors for collecting at least non-engine status and diagnostic information; a processor for processing at least information collected by the plurality of engine sensory monitors and the plurality of non-engine sensory monitors; and a plurality of communication interfaces for interfacing with a service system for the purpose of transmitting the processed information to the external service system.

Abstract: A BIST function is provided in which both the routing area devoted to the test signals and the area devoted to the circuits required to implement the BIST routines are minimized, while also including the ability to test a plurality of embedded memories at full speed in parallel. Testing the memories at full speed both reduces test time and improves the quality of the testing.

Abstract: A BIST function is provided in which both the row address and the column address of a memory to be tested may be selected independently. The present invention provides flexibility in selecting addresses to be tested, improves transition time between rows, and allows determination of which memory address passes or fails the test.

Abstract: A method and apparatus are provided for automatically generating the design of a BIST for embedded memories of an IC. The approach relies on counters or pseudo-random generators for the implementation of many of the functions. The invention incorporates software that generates equations that can be used as inputs to a logic synthesis tool. The output of the synthesis tool feeds an automatic routing tool where it is merged with the output of the synthesis of the other portions of the integrated circuit, IC. The routing tool places and routes the signals through the logic described by the synthesis tool along with the remainder of the IC. The result is a completed IC design that includes efficient memory BIST circuitry.

Abstract: A built-in self test (BIST) circuit for an integrated circuit tests one or more embedded memories by writing data to each memory address, reading it back out, and then comparing the input and output data to see if they match. The BIST circuit includes one or more data generators for supplying a sequence of data to be written to the various addresses of each memory and one or more identical address generators, each for supplying addresses to a separate embedded memory during read and write operations. Though the memories may have differently sized address spaces, all address generators generate a similar address sequence having a range of address values as large or larger than the address space of the largest memory. During each memory write cycle, a separate filter checks the address output of each address generator to determine whether the address is within the address space of the corresponding memory. If so, the BIST circuit writes the current data output of a data generator to that address of the memory.

Abstract: A method and circuit are provided for generating a minimum-sized address filter to detect when the address space of an embedded memory having a smaller address space than another larger embedded memory is being exceeded. The method includes decomposing a maximum address into alternating sequences of consecutive binary ones (1's) and zeros (0's), discarding a final sequence if it contains binary 1's, and generating a filter circuit from a filter function formed from the alternating sequences of consecutive binary 1's and 0's. A built-in self test (BIST) circuit incorporating the address filter provides the ability to test a plurality of embedded memories at full speed in parallel. A computer system including a computer program for generating the filter circuit may also be provided.