Patents by Inventor Yezdi Antia

Yezdi Antia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6349120
    Abstract: A method for improving spectral sampling using Discrete Fourier Transforms in a processor to detect a continuous wave (CW) signal in a burst having large initial uncertainties comprises the steps of dividing the burst into smaller sub-bursts; performing a Discrete Fourier Transform on each sub-burst; and non-coherently combining each sub-burst. A further variation includes selecting an optimal number L of sub-bursts based upon system performance, and desired detection performance at a minimum operating signal to noise ratio.
    Type: Grant
    Filed: December 4, 1998
    Date of Patent: February 19, 2002
    Assignee: Hughes Electronics Corporation
    Inventors: Zhen-Liang Shi, Yezdi Antia, A. Roger Hammons, Jr.
  • Patent number: 6347124
    Abstract: A system and method of soft decision decoding is disclosed. An average signal magnitude is generated from a plurality of message bits. A scale factor is generated in accordance with the average signal magnitude, and soft decision bits are generated by processing the message bits using the scale factor. The scale factor and soft decision bits are transmitted and received across a communication link. The soft decision bits are rescaled using the scale factor and then rounded to the nearest integer value. The rounded values are then decoded. The soft decision bits are generated using a quantization having at least two bits, and soft decision bits are preferably rescaled using at least five bits.
    Type: Grant
    Filed: October 29, 1998
    Date of Patent: February 12, 2002
    Assignee: Hughes Electronics Corporation
    Inventors: Yezdi Antia, Ludong Wang, Mohammad Soleimani, A. Roger Hammons
  • Publication number: 20020012363
    Abstract: A method and system for tracking a time division multiplexed synchronization signal in a satellite communication system is provided. The signal is provided as a series of frames with beacon signals time division multiplexed into at least one time slot of each frame. The beacon signal in each frame comprises a unique word sequence, which is the same in each frame, and a portion of a PN sequence. The entire PN sequence is distributed into a plurality of frames forming a superframe. Frequency variations of the incoming signal are tracked at the satellite terminal by correlating the PN sequence of the incoming signal against early and late locally generated versions of the PN sequence in a discriminate circuit. The output of the discriminate is provided to a delay locked loop circuit of at least third order. The output of the loop is used to adjust the frequency of the VCO, which clocks the A/D converter operating on the incoming signal.
    Type: Application
    Filed: January 24, 2001
    Publication date: January 31, 2002
    Inventors: Bassel Beidas, Olga Ritterbush, Stanley Kay, Yezdi Antia, Bala Subramaniam
  • Patent number: 6182251
    Abstract: A method of channel estimation in a wireless communication system has steps of receiving a data burst comprising a plurality of portions of known data, and remaining data that is unknown; comparing reference data to each of the plurality of portions of known data and determining error for each of the portions of known data; averaging the determined error for predetermined ones of the portions of known data; and estimating error for at least a portion of the remaining data as a function of the determined error having been averaged.
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: January 30, 2001
    Assignee: Hughes Electronics Corporation
    Inventors: Moe Rahnema, Zhen-Liang Shi, Ludong Wang, Yezdi Antia, Mohammad Soleimani
  • Patent number: 6031474
    Abstract: A novel code and method of code construction is disclosed. The disclosed code is a half rate block code designed to function optimally in a Raleigh fading channel. The disclosed code and method may be implemented in an 8-ARY QPSK modulation system. An alternative embodiment is a code and method of code construction for use in a 16-ARY QPSK modulation system. Both codes are systematic and use four symbols to represent two symbols. The first two symbols of the code are the information symbols. The second two symbols are parity symbols. The parity symbols are selected to provide maximum Euclidean distance between code words.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: February 29, 2000
    Inventors: Stanley E. Kay, Yezdi Antia, Andrew J. Macdonald
  • Patent number: 5677919
    Abstract: A receiver in a digital cellular communication system includes a system for receiving a signal transmitted in the cellular system and representing a code word encoded in a binary linear block code and a first digital signal processor for demodulating the signal and a second digital signal processor for decoding the binary linear block code in the demodulated signal. A system operates the digital signal processors to demodulate the code word partially and produce a demodulated portion of the code word, to provide a partial syndrome calculation to the demodulated portion of the code word as at least one additional portion of the code word is demodulated, and to apply an additional syndrome calculation to the at least one additional demodulated portion of the code word, and to combine the partial and additional syndrome calculations to provide a complete syndrome calculation. An output system then outputs decoded signals.
    Type: Grant
    Filed: June 10, 1994
    Date of Patent: October 14, 1997
    Assignee: Hughes Electronics
    Inventor: Yezdi Antia
  • Patent number: 5390215
    Abstract: Demodulation is provided for a base station receiver in a cellular communication system by a demodulator having four data linked digital signal processors. An MLSE equalizer and maximal ratio combiner for diversity paths includes multiple components that are partitioned among the processors for pipelined execution with predetermined time ordering.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: February 14, 1995
    Assignee: Hughes Aircraft Company
    Inventors: Yezdi Antia, Youngky Kim, Hiep Pham