Patents by Inventor Yezdi Dordi

Yezdi Dordi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230298936
    Abstract: An electrically conductive structure in an integrated circuit (IC) includes recessed features in a dielectric layer filled with metal. The recessed features include a conformal, self-forming diffusion barrier and seed layer to limit oxidation of the metal into ions that will diffuse through the dielectric.
    Type: Application
    Filed: August 10, 2021
    Publication date: September 21, 2023
    Inventors: Kyle Jordan Blakeney, Yezdi Dordi
  • Publication number: 20220415819
    Abstract: A metal interconnect structure is doped with zinc, indium, or gallium using top-down doping processes to improve diffusion barrier properties with minimal impact on line resistance. Dopant is introduced prior to metallization or after metallization. Dopant may be introduced by chemical vapor deposition on a liner layer at an elevated temperature prior to metallization, by chemical vapor deposition on a metal feature at an elevated temperature after metallization, or by electroless deposition on a copper feature after metallization. Application of elevated temperatures causes the metal interconnect structure to be doped and form a self-formed barrier layer or strengthen an existing diffusion barrier layer.
    Type: Application
    Filed: November 20, 2020
    Publication date: December 29, 2022
    Inventors: Aniruddha JOI, Dries DICTUS, Yezdi DORDI
  • Patent number: 11225714
    Abstract: A method is provided, including the following operations: depositing a liner in a feature of a substrate; depositing a monolayer of zinc over the liner; after depositing the monolayer of zinc, performing a thermal treatment on the substrate, wherein the thermal treatment is configured to cause migration of the zinc to an interface of the liner and an oxide layer of the substrate, the migration of the zinc producing an adhesive barrier at the interface that improves adhesion between the liner and the oxide layer of the substrate; repeating the operations of depositing the monolayer of zinc and performing the thermal treatment until a predefined number of cycles is reached.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: January 18, 2022
    Assignee: Lam Research Corporation
    Inventors: Kailash Venkatraman, Yezdi Dordi, Aniruddha Joi
  • Publication number: 20210166971
    Abstract: A method for forming a self-forming barrier in a feature of a substrate is provided, including the following operations: depositing a metallic liner in the feature of the substrate, the metallic liner being deposited over a dielectric of the substrate; depositing a zinc-containing precursor over the metallic liner; performing a thermal soak of the substrate; repeating the depositing of the zinc-containing precursor and the thermal soak of the substrate for a predefined number of cycles; wherein the method forms a zinc-containing barrier layer at an interface between the metallic liner and the dielectric.
    Type: Application
    Filed: June 28, 2019
    Publication date: June 3, 2021
    Inventors: Aniruddha Joi, Dries Dictus, Yezdi Dordi
  • Patent number: 10640874
    Abstract: A method of performing electroless electrochemical atomic layer deposition is provided and includes: providing a substrate including an exposed upper metal layer; exposing the substrate to a first precursor solution to create a sacrificial metal monolayer on the exposed upper metal layer via underpotential deposition, where the first precursor solution is an aqueous solution including a reducing agent; subsequent to the forming of the sacrificial metal monolayer, rinsing the substrate; subsequent to the rinsing of the substrate, exposing the substrate to a second precursor solution to replace the sacrificial metal monolayer with a first deposition layer; and subsequent to replacing the sacrificial metal monolayer with the first deposition layer, rinsing the substrate. The exposure of the substrate to the first precursor solution and the exposure of the substrate to the second precursor solution are electroless processes.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: May 5, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Aniruddha Joi, Kailash Venkatraman, Yezdi Dordi
  • Publication number: 20200063256
    Abstract: A method is provided, including the following operations: depositing a liner in a feature of a substrate; depositing a monolayer of zinc over the liner; after depositing the monolayer of zinc, performing a thermal treatment on the substrate, wherein the thermal treatment is configured to cause migration of the zinc to an interface of the liner and an oxide layer of the substrate, the migration of the zinc producing an adhesive barrier at the interface that improves adhesion between the liner and the oxide layer of the substrate; repeating the operations of depositing the monolayer of zinc and performing the thermal treatment until a predefined number of cycles is reached.
    Type: Application
    Filed: October 31, 2019
    Publication date: February 27, 2020
    Inventors: Kailash Venkatraman, Yezdi Dordi, Aniruddha Joi
  • Patent number: 10508351
    Abstract: Layer-by-layer thickness control of an electroplated film can be achieved by using a cyclic deposition process. The cyclic process involves forming a layer (or partial layer) of hydrogen on a surface of the substrate, then displacing the layer of hydrogen with a layer of metal. These steps are repeated a number of times to deposit the metal film to a desired thickness. Each step in the cycle is self-limiting, thereby enabling atomic level thickness control.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: December 17, 2019
    Assignee: Lam Research Corporation
    Inventors: Aniruddha Joi, Yezdi Dordi
  • Patent number: 10501846
    Abstract: A method is provided, including the following operations: depositing a ruthenium liner in a feature of a substrate; depositing a monolayer of zinc over the ruthenium liner; after depositing the monolayer of zinc, performing a thermal treatment on the substrate, wherein the thermal treatment is configured to cause migration of the zinc to an interface of the ruthenium liner and an oxide layer of the substrate, the migration of the zinc producing an adhesive barrier at the interface that improves adhesion between the ruthenium liner and the oxide layer of the substrate; repeating the operations of depositing the monolayer of zinc and performing the thermal treatment until a predefined number of cycles is reached.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: December 10, 2019
    Assignee: Lam Research Corporation
    Inventors: Kailash Venkatraman, Yezdi Dordi, Aniruddha Joi
  • Publication number: 20190363048
    Abstract: An electrically conductive structure in an integrated circuit (IC) includes a bottom metal line and a top metal line with via providing electrical interconnection between the bottom metal line and the top metal line. The via is fully aligned with both the bottom metal line and the top metal line. An electrically conductive material fills an opening formed in a dielectric material to form the via, and the electrically conductive material is directly in contact with the bottom metal line. No diffusion barrier layer and/or liner layer is between the bottom metal line and the via.
    Type: Application
    Filed: May 22, 2018
    Publication date: November 28, 2019
    Inventors: Lie Zhao, Artur Kolics, Yezdi Dordi
  • Patent number: 10483163
    Abstract: A method is provided, including the following operations: performing a deposition process on a substrate, the deposition process configured to deposit a ruthenium layer in a feature on the substrate, the ruthenium layer being doped with zinc at an atomic percentage less than approximately 30 percent; after depositing the ruthenium layer, annealing the substrate, wherein the annealing is configured to cause migration of the zinc to an interface of the ruthenium layer and an oxide layer of the substrate, the migration of the zinc producing an adhesive barrier at the interface that inhibits electromigration of the ruthenium layer.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 19, 2019
    Assignee: Lam Research Corporation
    Inventors: Aniruddha Joi, Yezdi Dordi
  • Publication number: 20190122922
    Abstract: A method is provided, including the following operations: performing a deposition process on a substrate, the deposition process configured to deposit a ruthenium layer in a feature on the substrate, the ruthenium layer being doped with zinc at an atomic percentage less than approximately 30 percent; after depositing the ruthenium layer, annealing the substrate, wherein the annealing is configured to cause migration of the zinc to an interface of the ruthenium layer and an oxide layer of the substrate, the migration of the zinc producing an adhesive barrier at the interface that inhibits electromigration of the ruthenium layer.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 25, 2019
    Inventors: Aniruddha Joi, Yezdi Dordi
  • Patent number: 10262943
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: April 16, 2019
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Publication number: 20190078202
    Abstract: A method is provided, including the following operations: depositing a ruthenium liner in a feature of a substrate; depositing a monolayer of zinc over the ruthenium liner; after depositing the monolayer of zinc, performing a thermal treatment on the substrate, wherein the thermal treatment is configured to cause migration of the zinc to an interface of the ruthenium liner and an oxide layer of the substrate, the migration of the zinc producing an adhesive barrier at the interface that improves adhesion between the ruthenium liner and the oxide layer of the substrate; repeating the operations of depositing the monolayer of zinc and performing the thermal treatment until a predefined number of cycles is reached.
    Type: Application
    Filed: September 11, 2017
    Publication date: March 14, 2019
    Inventors: Kailash Venkatraman, Yezdi Dordi, Aniruddha Joi
  • Publication number: 20190048472
    Abstract: A method of performing electroless electrochemical atomic layer deposition is provided and includes: providing a substrate including an exposed upper metal layer; exposing the substrate to a first precursor solution to create a sacrificial metal monolayer on the exposed upper metal layer via underpotential deposition, where the first precursor solution is an aqueous solution including a reducing agent; subsequent to the forming of the sacrificial metal monolayer, rinsing the substrate; subsequent to the rinsing of the substrate, exposing the substrate to a second precursor solution to replace the sacrificial metal monolayer with a first deposition layer; and subsequent to replacing the sacrificial metal monolayer with the first deposition layer, rinsing the substrate. The exposure of the substrate to the first precursor solution and the exposure of the substrate to the second precursor solution are electroless processes.
    Type: Application
    Filed: August 3, 2018
    Publication date: February 14, 2019
    Inventors: Aniruddha Joi, Kailash Venkatraman, Yezdi Dordi
  • Publication number: 20180374747
    Abstract: A method is provided, including the following operations: performing a deposition process on a substrate, the deposition process configured to deposit a copper layer in a feature on the substrate, the copper layer being doped with zinc at an atomic percentage less than approximately 30 percent; after depositing the copper layer, annealing the substrate, wherein the annealing is configured to cause migration of the zinc to an interface of the copper layer and an oxide layer of the substrate, the migration of the zinc producing an adhesive barrier at the interface that inhibits electromigration of the copper layer.
    Type: Application
    Filed: June 27, 2017
    Publication date: December 27, 2018
    Inventors: Aniruddha Joi, Yezdi Dordi
  • Patent number: 10163695
    Abstract: A method is provided, including the following operations: performing a deposition process on a substrate, the deposition process configured to deposit a copper layer in a feature on the substrate, the copper layer being doped with zinc at an atomic percentage less than approximately 30 percent; after depositing the copper layer, annealing the substrate, wherein the annealing is configured to cause migration of the zinc to an interface of the copper layer and an oxide layer of the substrate, the migration of the zinc producing an adhesive barrier at the interface that inhibits electromigration of the copper layer.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: December 25, 2018
    Assignee: Lam Research Corporation
    Inventors: Aniruddha Joi, Yezdi Dordi
  • Publication number: 20180266001
    Abstract: Layer-by-layer thickness control of an electroplated film can be achieved by using a cyclic deposition process. The cyclic process involves forming a layer (or partial layer) of hydrogen on a surface of the substrate, then displacing the layer of hydrogen with a layer of metal. These steps are repeated a number of times to deposit the metal film to a desired thickness. Each step in the cycle is self-limiting, thereby enabling atomic level thickness control.
    Type: Application
    Filed: March 6, 2018
    Publication date: September 20, 2018
    Inventors: Aniruddha Joi, Yezdi Dordi
  • Publication number: 20180151503
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Application
    Filed: January 23, 2018
    Publication date: May 31, 2018
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Patent number: 9875968
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: January 23, 2018
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Publication number: 20170162512
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 8, 2017
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi