Patents by Inventor Yi-An Lai

Yi-An Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12001246
    Abstract: A display control method applicable to an all-in-one (AIO) computer is provided. The AIO computer includes a first monitor and a second monitor. The display control method includes: receiving a control instruction from the first monitor; projecting a display content on the second monitor according to the control instruction; and selectively enabling a touch control function of the second monitor according to the control instruction.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: June 4, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Yuni Lai, Jen-Chiu Chiang, Meng-Ru He, Chung-Shang Chi, Jia-Jung Kuo, Hsueh-Chih Tang, Shu-Yun Chen, Chun-Yen Huang, Chi-Rong Hsu, Yi-Ting Chen
  • Publication number: 20240176400
    Abstract: A portable keyboard assembly and an electronic device are provided. The portable keyboard assembly includes a keyboard body, a handle, and a docking station. The keyboard body includes a first side and a second side that are opposite to each other. The handle is integrally formed at the first side. The handle includes a gripping portion, and a thickness of any part of the gripping portion is greater than a thickness of the keyboard body. The docking station is pivotally connected to the keyboard body. The docking station has a slot. The electronic device includes the portable keyboard assembly and a display device. The display device is detachably inserted into the slot.
    Type: Application
    Filed: April 10, 2023
    Publication date: May 30, 2024
    Inventors: SIN-YI LAI, SHI-LIANG ZHONG
  • Patent number: 11990111
    Abstract: A noise measuring device is provided. The noise measuring device includes a soundproof box, a sound receiving device, a holding device, and a driving device. The sound receiving device is disposed in the soundproof box. The holding device is disposed in the soundproof box and configured to hold a testing object. The driving device is connected with the soundproof box and configure to drive the soundproof box to rotate.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: May 21, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Sheng-Pin Su, Yuan-I Tseng, Che-Hung Lai, Chien-Yi Wang, Chuan-Te Chang
  • Patent number: 11990510
    Abstract: A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Ting Tsai, Chung-Wei Hung, Jung-Ting Chen, Ying-Hua Lai, Song-Bor Lee, Bor-Zen Tien
  • Patent number: 11990381
    Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
  • Publication number: 20240162833
    Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
  • Publication number: 20240161966
    Abstract: A planar magnetic component is arranged on a circuit board of a resonant converter, and the resonant converter includes a primary-side circuit and a secondary-side circuit. The planar magnetic component includes an inductor trace, a primary-side trace, a secondary-side trace, and an iron core assembly. The iron core assembly includes an inductor iron core and an iron core. The primary-side trace surrounds the first through hole in a first direction and surrounds the second through hole in a second direction to form an ?-shaped trace. The inductor trace is formed on the primary-side layer board and coupled to the primary-side trace, and two ends of the inductor trace form an input terminal and an output terminal of the planar magnetic component.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Sheng CHANG, Chien-An LAI, Yi-Hsun CHIU, Chun-Yu YANG
  • Publication number: 20240160828
    Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
  • Publication number: 20240161969
    Abstract: A planar magnetic component is arranged on a circuit board of a resonant converter, and the resonant converter includes a primary-side circuit and a secondary-side circuit. The planar magnetic component includes an inductor trace, an inductor iron core, and a current transformer trace. The inductor trace is arranged on the primary-side circuit and formed one layer board of the circuit board to serve as a resonant inductor coupled to the primary-side circuit. The inductor iron core includes a core pillar, and the core pillar penetrates a through hole of the circuit board, and the inductor trace surrounds the through hole. The current transformer trace is formed on the circuit board to serve as a current transformer coil coupled to the resonant inductor. The current transformer trace surrounds the through hole to form a common-core structure that shares the inductor iron core.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Hsun CHIU, Yi-Sheng CHANG, Chien-An LAI, Chia-Wei CHU
  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Publication number: 20240148904
    Abstract: Synthetic nucleic acids encoding mini and microdystrophin genes comprising the membrane binding motifs or domains of the R10-R11-R12 region are provided. Also provided are vectors, host cells, and related methods of using the same to treat a subject suffering from Duchenne muscular dystrophy (DMD), Becker muscular dystrophy (BMD) or X-linked dilated cardiomyopathy (XLDC), or for ameliorating one or more adverse effects of DMD, BMD, or XLDC. Also provided are a fusion protein comprising a nNOS binding domain of dystrophin R16-R17 that is operably linked to a syntrophin PDZ domain and synthetic nucleic acids comprising the same that can be used to treat subjects with diseases characterized by loss of sarcolemmal neuronal nitric oxide synthase (nNOS) activity.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 9, 2024
    Inventors: Dongsheng Duan, Yi Lai, Junling Zhao, Yongping Yue
  • Publication number: 20240155185
    Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Inventors: Chia-Hao CHANG, You-Tsai JENG, Kai-Wen YEH, Yi-Cheng CHEN, Te-Chuan WANG, Kai-Wen CHENG, Chin-Lung LIN, Tai-Lai TUNG, Ko-Yin LAI
  • Patent number: 11977408
    Abstract: A multimedia system and a multimedia operation method are provided. The multimedia system includes a signal encoder, a screen, multiple loudspeakers, a processor, and an amplifier circuit. The signal encoder encodes an image signal, an audio signal, and an audio enhancement signal to provide a multimedia signal. The image signal is divided into multiple regional image signals based on multiple display regions. The audio signal includes multiple regional audio signals corresponding to the regional image signals. The processor extracts the image signal, the regional audio signals, and the audio enhancement signal from the multimedia signal and controls the screen to display the image signal. The amplifier circuit adjusts the regional audio signals in response to the audio enhancement signal and provides the adjusted regional audio signals to the loudspeakers.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: May 7, 2024
    Assignee: Wistron Corporation
    Inventors: Han-Yi Liu, Chang-Hsin Lai
  • Publication number: 20240136256
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes attaching a first die pad of a semiconductor die to a central pad of a package leadframe. The first die pad is located in a central region on an active side of the semiconductor die. A second die pad of the semiconductor die is connected a lead of the package lead frame. The second die pad is located in a periphery region on the active side of the semiconductor die. An encapsulant encapsulates a portion of the semiconductor die and a portion of the package leadframe. A backside surface of the semiconductor die is exposed at a top major surface of the encapsulant, and a backside surface of the central pad exposed at a bottom major surface of the encapsulant.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Inventors: Frank.zy Guo, Yi-Tien Liao, Sam Lai
  • Publication number: 20240128324
    Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Chung-Yi Chiu
  • Patent number: 11962847
    Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: April 16, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chia-Hao Chang, You-Tsai Jeng, Kai-Wen Yeh, Yi-Cheng Chen, Te-Chuan Wang, Kai-Wen Cheng, Chin-Lung Lin, Tai-Lai Tung, Ko-Yin Lai
  • Patent number: 11951233
    Abstract: Provided are methods of producing an acellular organ. The method includes the steps of, subjecting an organ derived from an animal to a static supercritical fluid (SCF) treatment followed by a dynamic SCF treatment. Optionally, the method of the present disclosure further includes a hypertonic and a hypotonic treatments prior to the static SCF treatment, and/or a neutralizing treatment after the dynamic SCF treatment. Also disclosed herein are acellular organs produced by the present method.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: April 9, 2024
    Assignee: ACRO BIOMEDICAL COMPANY. LTD.
    Inventors: Dar-Jen Hsieh, Chao-Yi Wei, Chao-Chin Chao, Jer-Cheng Kuo, Yi-Ping Lai, Srinivasan Periasamy
  • Patent number: 11955956
    Abstract: A switching circuit includes a main circuit including a number of first transistors. The main circuit has a first node, a second node, and a third node and is operative in response to a control signal received by the first node, and the second node is configured to receive a supply voltage. The switching circuit also includes an auxiliary circuit electrically coupled to the second node of the main circuit and configured to provide surge protection for the main circuit. The auxiliary circuit includes a second transistor. A breakdown voltage of the second transistor is different than a breakdown voltage of each first transistor of the number of first transistors.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-An Lai, Chan-Hong Chern, Cheng-Hsiang Hsieh
  • Publication number: 20240113071
    Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
  • Publication number: 20240113166
    Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.
    Type: Application
    Filed: February 15, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ging Lin, Chun-Liang Lai, Yun-Chen Wu, Ya-Yi Tsai, Shu-Yuan Ku, Shun-Hui Yang