Patents by Inventor Yi-Bin Hsieh
Yi-Bin Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8531216Abstract: The present invention discloses an electronic apparatus.Type: GrantFiled: July 24, 2012Date of Patent: September 10, 2013Assignee: Ralink Technology Corp.Inventors: Jin-Xiao Wu, Heng-Chih Lin, Yi-Bin Hsieh
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Patent number: 8502576Abstract: A charge pump circuit includes a charge generation circuit, a tracking circuit, a replica circuit, and a main charge pump. The main charge pump generates a charge current and a discharge current to a subsequent loop filter according to a UP signal and a DOWN signal. The replica circuit generates a first voltage in response to the current values of the first current source and the second current source of the main charge pump. The tracking circuit adjusts the current values of the first current source and the second current source of the main charge pump according to the first voltage and a second voltage, wherein the second voltage is in response to a voltage of an output node of the main charge pump.Type: GrantFiled: September 23, 2011Date of Patent: August 6, 2013Assignee: Ralink Technology CorporationInventor: Yi Bin Hsieh
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Publication number: 20120280744Abstract: A charge pump circuit includes a charge generation circuit, a tracking circuit, a replica circuit, and a main charge pump. The main charge pump generates a charge current and a discharge current to a subsequent loop filter according to a UP signal and a DOWN signal. The replica circuit generates a first voltage in response to the current values of the first current source and the second current source of the main charge pump. The tracking circuit adjusts the current values of the first current source and the second current source of the main charge pump according to the first voltage and a second voltage, wherein the second voltage is in response to a voltage of an output node of the main charge pump.Type: ApplicationFiled: September 23, 2011Publication date: November 8, 2012Applicant: RALINK TECHNOLOGY CORPORATIONInventor: Yi Bin HSIEH
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Patent number: 7999612Abstract: An operational amplifier includes an input stage for generating a first differential output signal pair according to a first differential input signal pair, an output stage for generating a second differential output signal pair according to at least a second differential input signal pair, and a high-pass filtering circuit coupled between the input stage and the output stage for performing high-pass filtering on the first differential output signal pair, for generating the at least a second differential input signal pair.Type: GrantFiled: January 27, 2010Date of Patent: August 16, 2011Assignee: Ralink Technology Corp.Inventor: Yi-Bin Hsieh
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Patent number: 7903017Abstract: A comparator for a pipelined ADC includes a sampling circuit coupled to a plurality of differential input voltages and a plurality of differential reference voltages, for sampling the plurality of differential input voltages according to a first clock signal and sampling the plurality of differential reference voltages according to a second clock signal, a preamplifier coupled to the sampling circuit comprising a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, for amplifying a voltage across the positive input terminal and the negative input terminal for generating a plurality of differential output voltages, and a latch circuit coupled to the preamplifier for latching the plurality of differential output voltages.Type: GrantFiled: August 28, 2009Date of Patent: March 8, 2011Assignee: Ralink Technology Corp.Inventors: Yi-Bin Hsieh, Heng-Chih Lin
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Publication number: 20110018633Abstract: An operational amplifier includes an input stage for generating a first differential output signal pair according to a first differential input signal pair, an output stage for generating a second differential output signal pair according to at least a second differential input signal pair, and a high-pass filtering circuit coupled between the input stage and the output stage for performing high-pass filtering on the first differential output signal pair, for generating the at least a second differential input signal pair.Type: ApplicationFiled: January 27, 2010Publication date: January 27, 2011Inventor: Yi-Bin Hsieh
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Publication number: 20110012765Abstract: A comparator for a pipelined ADC includes a sampling circuit coupled to a plurality of differential input voltages and a plurality of differential reference voltages, for sampling the plurality of differential input voltages according to a first clock signal and sampling the plurality of differential reference voltages according to a second clock signal, a preamplifier coupled to the sampling circuit comprising a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, for amplifying a voltage across the positive input terminal and the negative input terminal for generating a plurality of differential output voltages, and a latch circuit coupled to the preamplifier for latching the plurality of differential output voltages.Type: ApplicationFiled: August 28, 2009Publication date: January 20, 2011Inventors: Yi-Bin Hsieh, Heng-Chih Lin
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Patent number: 7683599Abstract: A voltage control circuit is provided. The voltage control circuit comprises a control voltage source, a current generating unit, and an output voltage generating unit. The control voltage source inputs a single end control voltage. The current generating unit coupled to the control voltage source and a ground generates a first current according to the single end control voltage. The output voltage generating unit coupled to the current generating unit, receives a reference voltage, and generates a first output voltage and a second output voltage according to the first current and the reference voltage. A value of the first output voltage is greater than a value of the second output voltage.Type: GrantFiled: May 25, 2007Date of Patent: March 23, 2010Assignee: Princeton Technology CorporationInventors: Hisn-Kuang Chen, Yi-Bin Hsieh, Che-Wei Hsu
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Patent number: 7567127Abstract: An automatic-gain control circuit includes a variable-gain amplifier, a peak-detecting circuit, and an adjustable charge/discharge circuit. The variable-gain amplifier receives an input signal and adjusts the input signal based on a gain-factor control signal for generating a corresponding output signal. The peak-detecting circuit is coupled to the variable-gain amplifier for generating a comparing signal according to a reference signal and the output signal. The adjustable charge/discharge circuit is coupled to the peak-detecting circuit and the variable-gain amplifier for outputting a charge current or a discharge current based on the comparing signal, thereby generating the gain-factor control signal. The ratio between the charge current and the discharge current is adjustable.Type: GrantFiled: December 5, 2006Date of Patent: July 28, 2009Assignee: Princeton Technology CorporationInventors: Yi-Bin Hsieh, Hisn-Kuang Chen, Che-Wei Hsu
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Patent number: 7532560Abstract: A signal processing circuit for adjusting an input signal and generating a corresponding digital output signal in an optical disk driver is provided. The signal processing circuit includes an attenuator for receiving and attenuating the input signal and then generating an attenuated output signal; a gain controllable amplifier for receiving and amplifying the input signal and then generating an amplified output signal; a control unit providing a control signal and a select signal, the control signal is directed to the attenuator and the gain controllable amplifier for enabling/disabling the attenuator and the gain controllable amplifier and for controlling their gains such that one of the attenuator and gain controllable amplifier is enabled at a time; and a waveform adjuster circuit for adjusting the amplified/attenuated output signal delivered from the gain controllable amplifier or the attenuator so as to generate the digital signal related to the input signal.Type: GrantFiled: February 24, 2005Date of Patent: May 12, 2009Assignee: VIA Technologies Inc.Inventors: Jyh-Fong Lin, Yi-Bin Hsieh, Chih-Chang Chien
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Publication number: 20080143306Abstract: A voltage control circuit is provided. The voltage control circuit comprises a control voltage source, a current generating unit, and an output voltage generating unit. The control voltage source inputs a single end control voltage. The current generating unit coupled to the control voltage source and a ground generates a first current according to the single end control voltage. The output voltage generating unit coupled to the current generating unit, receives a reference voltage, and generates a first output voltage and a second output voltage according to the first current and the reference voltage. A value of the first output voltage is greater than a value of the second output voltage.Type: ApplicationFiled: May 25, 2007Publication date: June 19, 2008Inventors: Hisn-Kuang Chen, Yi-Bin Hsieh, Che-Wei Hsu
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Publication number: 20080068087Abstract: An automatic-gain control circuit includes a variable-gain amplifier, a peak-detecting circuit, and an adjustable charge/discharge circuit. The variable-gain amplifier receives an input signal and adjusts the input signal based on a gain-factor control signal for generating a corresponding output signal. The peak-detecting circuit is coupled to the variable-gain amplifier for generating a comparing signal according to a reference signal and the output signal. The adjustable charge/discharge circuit is coupled to the peak-detecting circuit and the variable-gain amplifier for outputting a charge current or a discharge current based on the comparing signal, thereby generating the gain-factor control signal. The ratio between the charge current and the discharge current is adjustable.Type: ApplicationFiled: December 5, 2006Publication date: March 20, 2008Inventors: Yi-Bin Hsieh, Hisn-Kuang Chen, Che-Wei Hsu
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Patent number: 7333039Abstract: A cyclic pipeline analog to digital converter includes a dual mode sample and hold circuit, a multiplying digital to analog converter (MDAC), a sub-analog to digital converter (sub-ADC) and a decoder. The dual mode sample and hold circuit has a charge-redistribution mode and a flip-around mode. The dual mode sample and hold circuit receives first and second input voltages and first and second feedback voltages and generates a differential output signal pair. The MDAC receives the differential output signal pair and a digital multiplying word and generates the first and second feedback voltages. The sub-ADC receives the differential output signal pair and generates the digital multiplying word and a digital output word. The decoder converts the digital output word to a digital output corresponding to the first and second input voltages.Type: GrantFiled: October 2, 2006Date of Patent: February 19, 2008Assignee: Via Technologies, Inc.Inventors: Wu-Hung Lu, Yi-Bin Hsieh
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Publication number: 20070090984Abstract: A cyclic pipeline analog to digital converter includes a dual mode sample and hold circuit, a multiplying digital to analog converter (MDAC), a sub-analog to digital converter (sub-ADC) and a decoder. The dual mode sample and hold circuit has a charge-redistribution mode and a flip-around mode. The dual mode sample and hold circuit receives first and second input voltages and first and second feedback voltages and generates a differential output signal pair. The MDAC receives the differential output signal pair and a digital multiplying word and generates the first and second feedback voltages. The sub-ADC receives the differential output signal pair and generates the digital multiplying word and a digital output word. The decoder converts the digital output word to a digital output corresponding to the first and second input voltages.Type: ApplicationFiled: October 2, 2006Publication date: April 26, 2007Applicant: VIA TECHNOLOGIES, INC.Inventors: Wu-Hung Lu, Yi-Bin Hsieh
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Patent number: 7113029Abstract: Transconductance filter circuits. A transconductor includes two inputs for receiving two differential voltages, and a first output terminal and a second output terminal for outputting two differential signals. A first capacitor array includes at least one first switch capacitor unit controlled by a first signal, and a first equivalent capacitor coupled between the first output terminal and the second output terminal when the first signal is enabled. two second capacitor arrays each includes at least one second switch capacitor unit controlled by a second signal, two second equivalent capacitors respectively coupled between the first output terminal and a ground level, and between the second output terminal and the ground level when the second signal is enabled. The capacitance of the first equivalent capacitor exceeds that of the two second equivalent capacitors connected in serial.Type: GrantFiled: April 12, 2005Date of Patent: September 26, 2006Assignee: VIA Technologies Inc.Inventors: Yi-Bin Hsieh, Wen-Hui Chen
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Patent number: 7016450Abstract: A clock recovery circuit for generating an output signal that is synchronized with an input signal. The clock recovery circuit includes a charge pump, a first filter, an oscillator, a switch circuit, and a second filter. When the charge pump operates, the switch circuit will disconnect the first filter from the oscillator. Additionally, when the charge pump stops operating, the switch circuit will connect the first filter and the oscillator such that the oscillator adjusts a frequency or phase of the output signal according to the output voltage of the first filter.Type: GrantFiled: June 21, 2002Date of Patent: March 21, 2006Assignee: VIA Technologies Inc.Inventors: Jyh-Fong Lin, Hsin-Chieh Lin, Yi-Bin Hsieh
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Publication number: 20060006931Abstract: Transconductance filter circuits. A transconductor includes two inputs for receiving two differential voltages, and a first output terminal and a second output terminal for outputting two differential signals. A first capacitor array includes at least one first switch capacitor unit controlled by a first signal, and a first equivalent capacitor coupled between the first output terminal and the second output terminal when the first signal is enabled. two second capacitor arrays each includes at least one second switch capacitor unit controlled by a second signal, two second equivalent capacitors respectively coupled between the first output terminal and a ground level, and between the second output terminal and the ground level when the second signal is enabled. The capacitance of the first equivalent capacitor exceeds that of the two second equivalent capacitors connected in serial.Type: ApplicationFiled: April 12, 2005Publication date: January 12, 2006Inventors: Yi-Bin Hsieh, Wen-Hui Chen
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Publication number: 20050280453Abstract: A phase locked loop circuit includes a loop filter having a first input terminal and a second input terminal and including a first capacitor coupled to the first terminal; a resistor having one terminal coupled to the first input terminal; a second capacitor coupled to the second input terminal; and a source follower having an input terminal coupled to the second input terminal and an output terminal coupled the other terminal of the resistor; a first charge pump coupled to the first input terminal outputting a first current; and a second charge pump coupled to the second input terminal outputting a second current; wherein the first current is a multiple of the second current.Type: ApplicationFiled: March 22, 2005Publication date: December 22, 2005Inventor: Yi-Bin Hsieh
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Patent number: 6927642Abstract: A duty cycle correction method converts a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle. The pulse signal has the same frequency as that of each of the differential analog signals. The duty cycle correction method processes the pair of differential analog signals into a first digital pulse signal and a second digital pulse signal, wherein the first digital pulse signal and the second digital pulse signal have a specified phase difference therebetween, frequency-divides the first digital pulse signal and the second digital pulse signal into a third digital pulse signal and a fourth digital pulse signal, and generates the output pulse signal according to the third and fourth digital pulse signals. The output pulse signal can be generated by performing an exclusive OR operation of the third and fourth digital pulse signals.Type: GrantFiled: March 26, 2004Date of Patent: August 9, 2005Assignee: Via Technologies, Inc.Inventor: Yi-Bin Hsieh
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Publication number: 20050157626Abstract: A signal processing circuit for adjusting an input signal and generating a corresponding digital output signal in an optical disk driver is provided. The signal processing circuit includes an attenuator for receiving and attenuating the input signal and then generating an attenuated output signal; a gain controllable amplifier for receiving and amplifying the input signal and then generating an amplified output signal; a control unit providing a control signal and a select signal, the control signal is directed to the attenuator and the gain controllable amplifier for enabling/disabling the attenuator and the gain controllable amplifier and for controlling their gains such that one of the attenuator and gain controllable amplifier is enabled at a time; and a waveform adjuster circuit for adjusting the amplified/attenuated output signal delivered from the gain controllable amplifier or the attenuator so as to generate the digital signal related to the input signal.Type: ApplicationFiled: February 24, 2005Publication date: July 21, 2005Inventors: Jyh-Fong Lin, Yi-Bin Hsieh, Chih-Chang Chien