Patents by Inventor Yi-Chang Sung
Yi-Chang Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200042291Abstract: A software system generating system comprises a specification generating module and a software system generating module wherein the software system generating module outputs a structured specification according to information being provided by user's demand; the software system generating module includes a plurality of predefined elements which each element is a programmable unit; the structured specification defines characteristics of the element to generate forms which the characteristic is a combination relationship of the plurality of predefined elements; after inputting the structured specification into the software system generating module and processing through a coding process, the software system generating module generates a system menu and its relevant links based on the analyzed system architecture to form a complete processing procedure; and the software system generating module complies and interprets the system program code combination to generate the result system.Type: ApplicationFiled: December 11, 2018Publication date: February 6, 2020Inventor: Yi Chang Sung
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Publication number: 20200042292Abstract: A specification generating module outputs a structured specification and includes a plurality of predefined element in which each element is a programmable unit. The specification generating module defines a characteristic of each element in which the characteristics is a combination of the elements to generate forms. The specification generating module includes a specification editing interface comprising sections of a project structure, a resource list and a specification editing area. The section of project structure is used to define an execution flow and a relationship of each form. The section of the resource list is to provide all the elements for review and selected for editing. The section of the specification editing area is used to define the characteristics among the elements including a function, a value, an attribute and an input-output interaction relationship of the selected elements.Type: ApplicationFiled: January 17, 2019Publication date: February 6, 2020Inventors: Ming Tze Kao, Tsui Lin Lin, Yi Chang Sung
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Publication number: 20200042290Abstract: A BOM (bill-of-material)-based structured software specification generating method is provided and includes the steps of: declaring a system architecture and an execution flow, declaring a plurality of elements, each of the elements being a programmable unit, generating a plurality of non-repetitive part numbers by a part number generator, each of the part numbers being correspondent to each of the elements which forming a plurality of forms, then both the system architecture and the execution flow representing the relationship between each two of the plurality of forms, defining characteristics of the plurality of elements for, and generating a BOM-based structured specification.Type: ApplicationFiled: August 2, 2018Publication date: February 6, 2020Inventors: Ming Tze Kao, Tsui Lin Lin, Yi Chang Sung
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Patent number: 8215890Abstract: A method and system for aligning robotic wafer transfer systems provides a wafer cassette having one or more wafer slots having portions covered with an electrically conductive material and a sensor that is in electrical communication with the electrically conductive material. When a wafer is loaded into a wafer cassette such as may be contained within a wafer transfer module such as a FOUP, an indication of position is delivered to the sensor which detects the alignment and indicates if the loaded wafer undesirably contacts either or both of the opposed grooves that form the wafer slot of the wafer cassette. An indication of the wafer's position may be provided from the sensor to a controller that delivers a signal for aligning the wafer transfer blade of the wafer transfer robot responsive to the signal indicative of position.Type: GrantFiled: March 12, 2009Date of Patent: July 10, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Shu Tseng, Yi-Chang Sung, Chia-Chi Tsao, Chih-Che Lin
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Publication number: 20100234992Abstract: A method and system for aligning robotic wafer transfer systems provides a wafer cassette having one or more wafer slots having portions covered with an electrically conductive material and a sensor that is in electrical communication with the electrically conductive material. When a wafer is loaded into a wafer cassette such as may be contained within a wafer transfer module such as a FOUP, an indication of position is delivered to the sensor which detects the alignment and indicates if the loaded wafer undesirably contacts either or both of the opposed grooves that form the wafer slot of the wafer cassette. An indication of the wafer's position may be provided from the sensor to a controller that delivers a signal for aligning the wafer transfer blade of the wafer transfer robot responsive to the signal indicative of position.Type: ApplicationFiled: March 12, 2009Publication date: September 16, 2010Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Shu TSENG, Yi-Chang SUNG, Chia-Chi TSAO, Chih-Che LIN
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Patent number: 7301604Abstract: A method and system for identifying a defocus wafer by mapping a topography of each wafer in a first wafer batch using a level sensor apparatus (100); calculating a focus spot deviation (402) from the data, the focus spot deviation (402) corresponding to a height by which a focus spot of a photo exposure module would be defocused by the topography; converting the focus spot deviation (402) to a corresponding wafer stage set point to which the photo exposure module is set, to focus the focus spot on each wafer in the wafer batch; and identifying a defocus wafer in the wafer batch, as a wafer having a topography that would defocus the focus spot, even when the photo exposure module is set to the wafer stage set point.Type: GrantFiled: February 25, 2004Date of Patent: November 27, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hung Lin, Louie Liu, Li-Kong Turn, Chi-Hung Liao, Ham-Ming Hsieh, Yi-Chang Sung, Hsin-Chun Chiang
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Patent number: 6975407Abstract: An improved method of wafer height mapping using a wafer level sensor eliminates or substantially minimizes the “spacing” in the wafer height mapping data usually caused by having an exposure field on a wafer whose width is less than the width of the measurement spot array of the wafer level sensor and also not being a multiple of the width of a single measurement spot. According to the improved method, the measurement spot array is first translated towards one edge of the exposure field and scanned. Then the measurement spot array is translated towards the other edge of the exposure field and scanned second time to map the area that was missed during the first mapping scan.Type: GrantFiled: May 19, 2004Date of Patent: December 13, 2005Assignee: Taiwan Semiconductor Manufacturing Co, Ltd.Inventors: Chun-Sheng Wang, Yi-Chang Sung, Chi-Hung Liao, Li-Kong Turn, Louie Liu
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Publication number: 20050259272Abstract: An improved method of wafer height mapping using a wafer level sensor eliminates or substantially minimizes the “spacing” in the wafer height mapping data usually caused by having an exposure field on a wafer whose width is less than the width of the measurement spot array of the wafer level sensor and also not being a multiple of the width of a single measurement spot. According to the improved method, the measurement spot array is first translated towards one edge of the exposure field and scanned. Then the measurement spot array is translated towards the other edge of the exposure field and scanned second time to map the area that was missed during the first mapping scan.Type: ApplicationFiled: May 19, 2004Publication date: November 24, 2005Inventors: Chun-Sheng Wang, Yi-Chang Sung, Chi-Hung Liao, Li-Kong Turn, Louie Liu
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Publication number: 20050185170Abstract: A method and system for identifying a defocus wafer by mapping a topography of each wafer in a first wafer batch using a level sensor apparatus (100); calculating a focus spot deviation (402) from the data, the focus spot deviation (402) corresponding to a height by which a focus spot of a photo exposure module would be defocused by the topography; converting the focus spot deviation (402) to a corresponding wafer stage set point to which the photo exposure module is set, to focus the focus spot on each wafer in the wafer batch; and identifying a defocus wafer in the wafer batch, as a wafer having a topography that would defocus the focus spot, even when the photo exposure module is set to the wafer stage set point.Type: ApplicationFiled: February 25, 2004Publication date: August 25, 2005Inventors: Chun-Hung Lin, Louie Liu, Li-Kong Turn, Chi-Hung Liao, Ham-Ming Hsieh, Yi-Chang Sung, Hsin-Chun Chiang