Patents by Inventor Yi-Cheih Chen

Yi-Cheih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10872870
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 22, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Publication number: 20190259723
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Patent number: 10325872
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: June 18, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Patent number: 9877386
    Abstract: A substrate structure is provided, including: a carrier having at least a wiring area defined and positioned on a portion of a surface of the carrier; a first insulating layer formed on the wiring area; a wiring layer formed on the first insulating layer formed on the wiring area; and a second insulating layer formed on the wiring area. Therefore, a contact surface between the carrier and the first and second insulating layers is reduced by reducing the areas of the first and second insulating layers, whereby a substrate warpage due to mismatch of coefficients of thermal expansion (CTE) is avoided. The present invention further provides a method of manufacturing the substrate structure as described above.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: January 23, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-An Chang, Sung-Huan Sun, Chien-Hung Wu, Yi-Cheih Chen, Wen-Kai Liao
  • Publication number: 20170309585
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Application
    Filed: July 10, 2017
    Publication date: October 26, 2017
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Patent number: 9735124
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: August 15, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Patent number: 9515007
    Abstract: A substrate structure includes: a substrate body defined with a layout area, a sealing member and a cutting area, the sealing member being adjacent to the layout area, and the cutting area being adjacent to the sealing member; a wiring layer formed on the layout area; an insulating layer formed on the layout area and the wiring layer; and a metal layer formed on the insulating layer and the layout area. The insulating layer is prevented from being delaminated due to the formation of the metal layer.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: December 6, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-An Chang, Sung-Huan Sun, Chien-Hung Wu, Yi-Cheih Chen, Wen-Kai Liao
  • Patent number: 9398689
    Abstract: A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and having a plurality of openings for correspondingly exposing the conductive pads; and a plurality of ring bodies formed in the openings and corresponding in position to edges of the conductive pads. As such, a plurality of conductive elements can be subsequently formed inside the ring bodies so as to be prevented by the ring bodies from expanding outward during a reflow process, thereby protecting the insulating layer from being compressed by the conductive elements and preventing cracking of the insulating layer.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: July 19, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-An Chang, Sung-Huan Sun, Wen-Kai Liao, Chien-Hung Wu, Yi-Cheih Chen
  • Publication number: 20160190039
    Abstract: A substrate structure includes: a substrate body defined with a layout area, a sealing member and a cutting area, the sealing member being adjacent to the layout area, and the cutting area being adjacent to the sealing member; a wiring layer formed on the layout area; an insulating layer formed on the layout area and the wiring layer; and a metal layer formed on the insulating layer and the layout area. The insulating layer is prevented from being delaminated due to the formation of the metal layer.
    Type: Application
    Filed: October 9, 2015
    Publication date: June 30, 2016
    Inventors: Cheng-An Chang, Sung-Huan Sun, Chien-Hung Wu, Yi-Cheih Chen, Wen-Kai Liao
  • Publication number: 20160190080
    Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.
    Type: Application
    Filed: December 2, 2015
    Publication date: June 30, 2016
    Inventors: Yi-Cheih Chen, Sung-Huan Sun, Cheng-An Chang, Chien-Hung Wu, Fu-Tang Huang
  • Publication number: 20160079148
    Abstract: A substrate structure is provided, including: a carrier having at least a wiring area defined and positioned on a portion of a surface of the carrier; a first insulating layer formed on the wiring area; a wiring layer formed on the first insulating layer formed on the wiring area; and a second insulating layer formed on the wiring area. Therefore, a contact surface between the carrier and the first and second insulating layers is reduced by reducing the areas of the first and second insulating layers, whereby a substrate warpage due to mismatch of coefficients of thermal expansion (CTE) is avoided. The present invention further provides a method of manufacturing the substrate structure as described above.
    Type: Application
    Filed: March 25, 2015
    Publication date: March 17, 2016
    Inventors: Cheng-An Chang, Sung-Huan Sun, Chien-Hung Wu, Yi-Cheih Chen, Wen-Kai Liao
  • Publication number: 20150214168
    Abstract: A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and having a plurality of openings for correspondingly exposing the conductive pads; and a plurality of ring bodies formed in the openings and corresponding in position to edges of the conductive pads. As such, a plurality of conductive elements can be subsequently formed inside the ring bodies so as to be prevented by the ring bodies from expanding outward during a reflow process, thereby protecting the insulating layer from being compressed by the conductive elements and preventing cracking of the insulating layer.
    Type: Application
    Filed: August 19, 2014
    Publication date: July 30, 2015
    Inventors: Cheng-An Chang, Sung-Huan Sun, Wen-Kai Liao, Chien-Hung Wu, Yi-Cheih Chen