Abstract: The invention discloses a multi-tube body adapter which is connected to a plurality of outer tubes for application to a digestive system and a respiratory system of a human body. The multi-tube body adapter includes a housing to form an accommodating space of the multi-chamber. The plurality of chambers is not in communication with each other. One end of the plurality of chambers respectively provides a connection port and the other end of the plurality of chambers is commonly connected to an extension having a plurality of openings. By connecting with the chamber, the connection port and the opening, a supply path for separately providing the supply path of the respiratory system and the digestive system can be formed.

Abstract: A driving method of a nonvolatile memory device including multiple memory planes includes following operations: precharging at least one word line and at least one bit line of a first memory plane; if the at least one word line and the at least one bit line of the first memory plane have been precharged for a first time length or to respective voltage thresholds, precharging at least one word line and at least one bit line of a second memory plane; conducting a first data operation to at least one memory cell of the first memory plane disposed at intersections of the at least one word line and the at least one bit line thereof; conducting a second data operation to at least one memory cell of the second memory plane disposed at intersections of the at least one word line and the at least one bit line thereof.

Abstract: In the disclosure, a scheduled route of a lot may be rescheduled to another fabrication tool performing the same fabrication processes as to expand the production line and throughput. The controlling method includes at least the following steps. The lot is scheduled with a predetermined route having a plurality of fabrication tools configured to process the lot with a plurality of fabrication processes in a sequence. The lot is monitored as the lot is being processed by the fabrication tools in each of the fabrication processes, and inspection data is generated for each fabrication process. The lot is rescheduled to another fabrication tool outside of the predetermined route for one of the fabrication processes according to a release rule and the inspection data.

Abstract: The present disclosure relates to a non-volatile memory and operating method thereof. The non-volatile memory includes multiple memory strings, multiple bit switch units, a memory operation circuit and multiple source switch units. The bit switch units are electrically connected to the memory strings. The memory operation circuit is electrically connected to the bit switch units to transmit a write signal to the memory unit strings. The source switch units are electrically connected to the memory string so that the memory strings receive a bias signal via the source switch unit. In a program mode, when a first bit switch unit of the bit switch units is turned on and a first memory strings receives the write signal through the first bit switch unit, the source switch units electrically connected to the other memory strings will be turned on.

Abstract: A radiation therapy system includes a radiation source, a processor, a flexible pressure sensing matrix, and a pressure sensing device. The radiation source emits a radiation beam to a target region of a patient for treatment. The processor is coupled to the radiation source for adjusting an incident angle and intensity of the radiation beam. The flexible pressure sensing matrix is placed at an object for detecting an amount of movement and an amount of rotation of the object. The pressure sensing device is coupled to the flexible pressure sensing matrix for receiving the amount of movement and the amount of rotation of the object. When the amount of movement or the amount of rotation exceeds a first preset amount, the processor controls the radiation source to suspend treatment.

Abstract: A method for treating addiction by therapeutic radiation including generating an original therapeutic plan according to a basic radiation dose; emitting radiation beams to a target area of an addict according to the original therapeutic plan, the target area comprising nucleus accumbens, the radiation beams based on the basic radiation dose capable of lowering an activity of the nucleus accumbens; and imaging the target area to detect whether the nucleus accumbens recover activity in a preset duration after the original therapeutic plan is completed. A detection of whether the nucleus accumbens recover activity is configured for determining a target radiation dose.

Abstract: A memory device is described with NAND strings and corresponding BL connected to SSL, a first power supply circuit, a second power supply circuit to distribute a higher supply voltage than the first power supply circuit, and a page buffer that generates program/inhibit outputs having a level between the first power supply voltage and a first reference voltage. Data line drivers drive nodes coupled to corresponding BL with a first voltage or a second voltage between the second power supply voltage and a second reference voltage. A data line driver includes a first switch transistor connected between the data line node and the second power supply circuit, a second switch transistor between the data line node and the second voltage reference, and a boost circuit to boost the gate of the first switch transistor above the first supply voltage level to turn on the first switch transistor.

Abstract: A positioning system for positioning a body part of a patient for radiotherapy includes a positioning device and a radiation treatment system. The positioning device includes a photosensor disposed on an outer surface of the body part and configured to generate a sensing signal upon sensing a positioning beam. The processing unit is operable in a recording mode and a comparison mode. In the recording mode, the processing unit receives the sensing signal of the photosensor and generates reference positioning information according to the sensing signal. In the comparison mode, the processing unit receives the sensing signal of the photosensor and generates comparison positioning information according to the sensing signal. The processor compares the reference positioning information to the comparison positioning information and outputs a positioning result according to a result of comparison.

Abstract: A radiation measurement panel is disclosed. The radiation measurement panel comprising a substrate, a first conductive layer, a sacrificial layer, and a second conductive layer. The first conductive layer formed over the substrate. The sacrificial layer formed over the first conductive layer, wherein the dielectric constant of the sacrificial layer changes in accordance with a magnitude of received radiation. The second conductive layer formed over the sacrificial layer, wherein the magnitude of the received radiation corresponds to a capacitance between the first conductive layer and the second conductive layer.

Abstract: A memory device is described with NAND strings and corresponding BL connected to SSL, a first power supply circuit, a second power supply circuit to distribute a higher supply voltage than the first power supply circuit, and a page buffer that generates program/inhibit outputs having a level between the first power supply voltage and a first reference voltage. Data line drivers drive nodes coupled to corresponding BL with a first voltage or a second voltage between the second power supply voltage and a second reference voltage. A data line driver includes a first switch transistor connected between the data line node and the second power supply circuit, a second switch transistor between the data line node and the second voltage reference, and a boost circuit to boost the gate of the first switch transistor above the first supply voltage level to turn on the first switch transistor.

Abstract: A circuit for in-memory multiply-and-accumulate functions includes a plurality of NAND blocks. A NAND block includes an array of NAND strings, including B columns and S rows, and L levels of memory cells. W word lines are coupled to (B*S) memory cells in respective levels in the L levels. A source line is coupled to the (B*S) NAND strings in the block. String select line drivers supply voltages to connect NAND strings on multiple string select lines to corresponding bit lines simultaneously. Word line drivers are coupled to apply word line voltages to a word line or word lines in a selected level. A plurality of bit line drivers apply input data to the B bit lines simultaneously. A current sensing circuit is coupled to the source line.

Abstract: A memory device comprising: a memory cell array and a memory controller configured to program data to memory cells during a programming cycle using operations comprising: during a setup stage, providing a first voltage level to word lines, a second voltage level to a first dummy word line, and a fourth voltage level to second dummy word lines being different from the first dummy word line, wherein the first voltage level is lower than a threshold voltage of a first transistor coupled to the first dummy word line and the second voltage level and the fourth voltage are higher than the threshold voltage, during a program stage, providing a third voltage level to first word lines to program data to memory cells coupled to the first word lines, the second voltage level to the first dummy word line, and the fourth voltage level to the second dummy word lines.

Abstract: A memory device and a control method thereof are provided. The memory device includes I memory blocks, I global power lines and I first local driver modules. Each memory block includes M gate control lines and a plurality of transistor units arranged in M rows. Gates of the transistor units in the m-th row are electrically connected to the m-th gate control line. The I global power lines are electrically connected to I pre-driver circuits and the I memory blocks, respectively. Each first local driver module is electrically connected to one global power line and one memory block. Each first local driver module includes M first local driver circuits. The m-th first local driver circuit is electrically connected to the m-th gate control line.

Abstract: A memory device comprising: a memory cell array and a memory controller configured to program data to memory cells during a programming cycle using operations comprising: during a setup stage, providing a first voltage level to word lines, a second voltage level to a first dummy word line, and a fourth voltage level to second dummy word lines being different from the first dummy word line, wherein the first voltage level is lower than a threshold voltage of a first transistor coupled to the first dummy word line and the second voltage level and the fourth voltage are higher than the threshold voltage, during a program stage, providing a third voltage level to first word lines to program data to memory cells coupled to the first word lines, the second voltage level to the first dummy word line, and the fourth voltage level to the second dummy word lines.

Abstract: A memory device includes a memory array including a number of memory cell strings, a number of bit lines, a number of pre-charge circuits coupled to the memory cell strings, and a number of sense amplifier circuits coupled to the memory cell strings through the bit lines. Each memory cell string includes at least one first select transistor, a second select transistor and at least one memory cell. Each bit line includes a third select transistor, and is coupled to a memory cell string. During a pre-charging stage, the pre-charge circuits provide a first voltage to pre-charge the memory cell strings. During a programming stage, for the memory cell strings to be inhibited, the sense amplifier circuits provide a second voltage lower than the first voltage. For the memory cell strings to be programmed, the sense amplifier circuits provide a third voltage lower than the second voltage.

Abstract: A memory device includes a memory array including a number of memory cell strings, a number of bit lines, a number of pre-charge circuits coupled to the memory cell strings, and a number of sense amplifier circuits coupled to the memory cell strings through the bit lines. Each memory cell string includes at least one first select transistor, a second select transistor and at least one memory cell. Each bit line includes a third select transistor, and is coupled to a memory cell string. During a pre-charging stage, the pre-charge circuits provide a first voltage to pre-charge the memory cell strings. During a programming stage, for the memory cell strings to be inhibited, the sense amplifier circuits provide a second voltage lower than the first voltage. For the memory cell strings to be programmed, the sense amplifier circuits provide a third voltage lower than the second voltage.

Abstract: In the disclosure, a scheduled route of a lot may be rescheduled to another fabrication tool performing the same fabrication processes as to expand the production line and throughput. The controlling method includes at least the following steps. The lot is scheduled with a predetermined route having a plurality of fabrication tools configured to process the lot with a plurality of fabrication processes in a sequence. The lot is monitored as the lot is being processed by the fabrication tools in each of the fabrication processes, and inspection data is generated for each fabrication process. The lot is rescheduled to another fabrication tool outside of the predetermined route for one of the fabrication processes according to a release rule and the inspection data.

Abstract: A boost circuit includes a power rail to provide a supply voltage, a switch transistor controlling output of a boosted signal from a source of the switch transistor, and a timing and voltage control circuit configured to generate an equalization (EQ) signal to be applied to a gate of the switch transistor. The EQ waveform has a level being an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamped level between the EQ low level and the EQ high level.

Abstract: A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.

Abstract: A boost circuit includes a power rail to provide a supply voltage, a switch transistor controlling output of a boosted signal from a source of the switch transistor, and a timing and voltage control circuit configured to generate an equalization (EQ) signal to be applied to a gate of the switch transistor. The EQ waveform has a level being an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamped level between the EQ low level and the EQ high level.