Patents by Inventor Yi-Ching Pao

Yi-Ching Pao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11757255
    Abstract: A method of forming a flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package comprising: forming a VCSEL pillar array; applying a dielectric layer to the VCSEL pillar array, the dielectric layer filling trenches in between pillars forming the VCSEL pillar array and covering the pillars; planarizing the VCSEL pillar array to remove the dielectric layer covering the pillars exposing a metal layer on a top surface of the pillars; applying a metal coating on the metal layer on a top surface of the pillars, the metal layer defining a contact pattern of the VCSEL pillar array; and applying solder on the metal coating to flip chip mount the VCSEL pillar array to a substrate package.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: September 12, 2023
    Assignee: OEpic Semiconductors, Inc.
    Inventor: Yi-Ching Pao
  • Patent number: 11424595
    Abstract: A backside Vertical Cavity Surface Emitting Laser (VCSEL) has a substrate. A first mirror device is formed on the substrate. An active region is formed on the first mirror device. A second mirror device is formed on the active region. A pillar is formed by directional Inductive Coupled Plasma-Reactive Ion Etcher (ICP-RIE). The pillar exposes a portion of the first mirror device, the active region and the second mirror device. A first metal contact is formed over a top section of the pillar. A second metal contact is formed on the substrate. An opening formed in the second metal contact and aligned with the pillar.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 23, 2022
    Assignee: OEPIC Semiconductors, Inc.
    Inventors: Yi-Ching Pao, Majid Riaziat, Ta-Chung Wu, Wilson Kyi, James Pao
  • Patent number: 11283240
    Abstract: A backside Vertical Cavity Surface Emitting Laser (VCSEL) has a substrate. A first mirror device is formed on the substrate. An active region is formed on the first mirror device. A second mirror device is formed on the active region. A pillar is formed by directional Inductive Coupled Plasma-Reactive Ion Etcher (ICP-RIE). The pillar exposes a portion of the first mirror device, the active region and the second mirror device. A first metal contact is formed over a top section of the pillar. A second metal contact is formed on the substrate. An opening formed in the second metal contact and aligned with the pillar.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: March 22, 2022
    Assignee: OEPIC SEMICONDUCTORS, INC.
    Inventors: Yi-Ching Pao, Majid Riaziat, Ta-Chung Wu, Wilson Kyi, James Pao
  • Patent number: 11264780
    Abstract: A flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package has a VCSEL pillar array. A first metal contact is formed over a top section of each pillar of the VCSEL pillar array. A second metal contact is formed on a back surface of the VCEL pillar array. An opening is formed in the second metal contact and aligned with the pillars of the VCSEL pillar array. Solder tip is applied on each pillar of the VCSEL pillar array to flip chip mount the VCSEL pillar array.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 1, 2022
    Assignee: OEPIC SEMICONDUCTORS, INC.
    Inventor: Yi-Ching Pao
  • Patent number: 11233377
    Abstract: A method of forming a flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package comprising: forming a VCSEL pillar array; applying a dielectric layer to the VCSEL pillar array, the dielectric layer filling trenches in between pillars forming the VCSEL pillar array and covering the pillars; planarizing the VCSEL pillar array to remove the dielectric layer covering the pillars exposing a metal layer on a top surface of the pillars; applying a metal coating on the metal layer on a top surface of the pillars, the metal layer defining a contact pattern of the VCSEL pillar array; and applying solder on the metal coating to flip chip mount the VCSEL pillar array to a substrate package.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: January 25, 2022
    Assignee: OEPIC SEMICONDUCTORS INC.
    Inventor: Yi-Ching Pao
  • Publication number: 20210396499
    Abstract: A target shooting tracking system has a first camera taking and recording images. An image processor receiving the images. The image processor performing image subtraction on the images to identified a latest marking on a target.
    Type: Application
    Filed: January 27, 2021
    Publication date: December 23, 2021
    Inventors: YI-CHING PAO, KEVIN PURDY, JAMES PAO, ERIC ZHU
  • Patent number: 11201251
    Abstract: A photodiode has a substrate. A mesa structure is formed on the substrate, wherein the mesa structure has an n region containing an n type dopant formed on the substrate, an intermediate region positioned on the n region and a p region formed on the intermediate region and containing a p type dopant. A contact is formed on a top surface of the mesa and attached to the p region. The contact is formed around an outer perimeter of the mesa. The mesa has a diameter of 30 um or less.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: December 14, 2021
    Assignee: OEPIC SEMICONDUCTORS, INC.
    Inventors: Yi-Ching Pao, Majid Riaziat, Ta-Chung Wu
  • Publication number: 20210245005
    Abstract: A method for generating feedback to a user practicing a skill comprises: providing a local platform for acquiring physical parameter data pertaining to motion and position of the user and motion and position of a golf club and a golf ball struck by the golf club during a golf swing by the user; transmitting via a network at least a portion of the physical parameter data of the motion and position of the golf club and the golf ball struck by the golf club during the golf swing and the physical parameter data associated with the motion and position of the user during the golf swing from the local platform to a machine learning analysis engine as input information; entering the input information into a machine learning model, the machine learning model having a set of rules and statistical techniques to learn patterns from the input data, and a model which is trained by using evolving training sets, wherein an initial training sets is formed from selected professional golf players physical and swing characterist
    Type: Application
    Filed: October 20, 2020
    Publication date: August 12, 2021
    Inventors: YI-CHING PAO, JAMES J. PAO
  • Publication number: 20200411703
    Abstract: A photodiode has a substrate. A mesa structure is formed on the substrate, wherein the mesa structure has an n region containing an n type dopant formed on the substrate, an intermediate region positioned on the n region and a p region formed on the intermediate region and containing a p type dopant. A contact is formed on a top surface of the mesa and attached to the p region. The contact is formed around an outer perimeter of the mesa. The mesa has a diameter of 30 um or less.
    Type: Application
    Filed: February 5, 2020
    Publication date: December 31, 2020
    Inventors: YI-CHING PAO, MAJID RIAZIAT, TA-CHUNG WU
  • Publication number: 20200368624
    Abstract: An online gaming system verifying data integrity has a server hosting an online game. At least one gaming simulator is wirelessly coupled to the server. Data integrity circuitry is coupled to the server and the at least one gaming simulator. The data integrity circuitry ensures that sensory data inputs from the at least one gaming simulator are free from intentional manipulation.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 26, 2020
    Inventors: YI-CHING PAO, JAMES PAO
  • Patent number: 10840106
    Abstract: A method of semiconductor device fabrication that enables fine-line geometry lithographic definition and small form-factor packaging comprises: forming contacts on a metal layer of the semiconductor device; applying a protective mask layer over active regions and surfaces of the contacts having rough surface morphology; planarizing a surface of the semiconductor device until the protective mask layer is removed and the surfaces of the contacts having rough surface morphology are planarized; and forming contact stacks on the surfaces of the contacts which are planarized.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: November 17, 2020
    Assignee: OEPIC SEMICONDUCTORS, INC.
    Inventors: Yi-Ching Pao, James Pao, Majid Riaziat, Ta-Chung Wu
  • Publication number: 20200358423
    Abstract: A method for forming a Bulk Acoustic Wave (BAW) structure comprises forming a piezoelectric material on a first substrate; applying a first metal layer on a top surface of the piezoelectric material; forming a metal pattern on a second substrate, the metal pattern forming a cavity pattern between raised areas of the metal pattern; attaching the first metal layer to a top area of the metal pattern forming a plurality of cavity areas; removing the first substrate; and applying a second metal layer on a bottom surface of the piezoelectric material.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 12, 2020
    Inventors: Yi-Ching Pao, Majid Riaziat, James Pao
  • Publication number: 20200343691
    Abstract: A method of forming a Tunnel Junction (TJ) Vertical Cavity Surface Emitting Laser (VCSEL) array comprises forming a first mirror device on a substrate; forming an active region on the first mirror device; forming a first portion of a second mirror device on the active region; forming a plurality of tunnel junctions on the first portion of the second mirror device; and forming a second portion of the second mirror device through an epitaxial overgrowth, the second portion of the second mirror device covering the plurality of tunnel junctions, wherein individual VCSEL elements of the TJ VCSEL array are electrically connected through the epitaxial overgrowth of the second portion of the second mirror device.
    Type: Application
    Filed: July 9, 2020
    Publication date: October 29, 2020
    Inventors: MAJID RIAZIAT, YI-CHING PAO, TA-CHUNG WU
  • Publication number: 20200220328
    Abstract: A method of forming a flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package comprising: forming a VCSEL pillar array; applying a dielectric layer to the VCSEL pillar array, the dielectric layer filling trenches in between pillars forming the VCSEL pillar array and covering the pillars; planarizing the VCSEL pillar array to remove the dielectric layer covering the pillars exposing a metal layer on a top surface of the pillars; applying a metal coating on the metal layer on a top surface of the pillars, the metal layer defining a contact pattern of the VCSEL pillar array; and applying solder on the metal coating to flip chip mount the VCSEL pillar array to a substrate package.
    Type: Application
    Filed: March 19, 2020
    Publication date: July 9, 2020
    Inventor: YI-CHING PAO
  • Publication number: 20200220327
    Abstract: A backside Vertical Cavity Surface Emitting Laser (VCSEL) has a substrate. A first mirror device is formed on the substrate. An active region is formed on the first mirror device. A second mirror device is formed on the active region. A pillar is formed by directional Inductive Coupled Plasma-Reactive Ion Etcher (ICP-RIE). The pillar exposes a portion of the first mirror device, the active region and the second mirror device. A first metal contact is formed over a top section of the pillar. A second metal contact is formed on the substrate. An opening formed in the second metal contact and aligned with the pillar.
    Type: Application
    Filed: March 16, 2020
    Publication date: July 9, 2020
    Inventors: YI-CHING PAO, MAJID RIAZIAT, TA-CHUNG WU, WILSON KYI, JAMES PAO
  • Publication number: 20200118832
    Abstract: A method of semiconductor device fabrication that enables fine-line geometry lithographic definition and small form-factor packaging comprises: forming contacts on a metal layer of the semiconductor device; applying a protective mask layer over active regions and surfaces of the contacts having rough surface morphology; planarizing a surface of the semiconductor device until the protective mask layer is removed and the surfaces of the contacts having rough surface morphology are planarized; and forming contact stacks on the surfaces of the contacts which are planarized
    Type: Application
    Filed: October 7, 2019
    Publication date: April 16, 2020
    Inventors: YI-CHING PAO, JAMES PAO, MAJID RIAZIAT, TA-CHUNG WU
  • Publication number: 20190386464
    Abstract: An opto-electronic device has a backside Vertical Cavity Surface Emitting Laser (VCSEL) device. An optical component is formed on a rear surface of the backside VCSEL device.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 19, 2019
    Inventors: YI-CHING PAO, MAJID RIAZIAT, TA-CHUNG WU, WILSON KYI, JAMES PAO
  • Publication number: 20190260354
    Abstract: A Bulk Acoustic Resonator (BAR) structure has a substrate. A cavity pattern is formed on the substrate. A Bulk Acoustic Wave (BAW) structure is formed on the cavity pattern and the substrate, wherein portions of the cavity pattern are exposed. The cavity pattern under the BAW structure is removed creating a self-sustaining cavity to form the novel cavity structure.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 22, 2019
    Inventors: YI-CHING PAO, MAJID RIAZIAT, JAMES PAO
  • Publication number: 20190252858
    Abstract: A method of forming a Tunnel Junction (TJ) Vertical Cavity Surface Emitting Laser (VCSEL) array comprises forming a first mirror device on a substrate; forming an active region on the first mirror device; forming a first portion of a second mirror device on the active region; forming a plurality of tunnel junctions on the first portion of the second mirror device; and forming a second portion of the second mirror device through an epitaxial overgrowth, the second portion of the second mirror device covering the plurality of tunnel junctions, wherein individual VCSEL elements of the TJ VCSEL array are electrically connected through the epitaxial overgrowth of the second portion of the second mirror device.
    Type: Application
    Filed: February 12, 2019
    Publication date: August 15, 2019
    Inventors: MAJID RIAZIAT, YI-CHING PAO, TA-CHUNG WU
  • Publication number: 20190237936
    Abstract: A method of forming a flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package comprising: forming a VCSEL pillar array; applying a dielectric layer to the VCSEL pillar array, the dielectric layer filling trenches in between pillars forming the VCSEL pillar array and covering the pillars; planarizing the VCSEL pillar array to remove the dielectric layer covering the pillars exposing a metal layer on a top surface of the pillars; applying a metal coating on the metal layer on a top surface of the pillars, the metal layer defining a contact pattern of the VCSEL pillar array; and applying solder on the metal coating to flip chip mount the VCSEL pillar array to a substrate package.
    Type: Application
    Filed: January 28, 2019
    Publication date: August 1, 2019
    Inventor: YI-CHING PAO