Patents by Inventor Yi-Chuen Eng
Yi-Chuen Eng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097038Abstract: A semiconductor device, including a substrate, a first source/drain region, a second source/drain region, and a gate structure, is provided. The substrate has an extra body portion and a fin protruding from a top surface of the substrate, wherein the fin spans the extra body portion. The first source/drain region and the second source/drain region are in the fin. The gate structure spans the fin, is located above the extra body portion, and is located between the first source/drain region and the second source/drain region.Type: ApplicationFiled: October 13, 2022Publication date: March 21, 2024Applicant: United Microelectronics Corp.Inventors: Yi Chuen Eng, Tzu-Feng Chang, Teng-Chuan Hu, Yi-Wen Chen, Yu-Hsiang Lin
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Patent number: 10068979Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.Type: GrantFiled: August 15, 2017Date of Patent: September 4, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi Chuen Eng, Teng-Chuan Hu, I-Chang Wang, Wei-Chih Chen, Hsiu-Kuan Hsu
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Patent number: 9923071Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.Type: GrantFiled: August 21, 2017Date of Patent: March 20, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi Chuen Eng, Teng-Chuan Hu, I-Chang Wang, Wei-Chih Chen, Hsiu-Kuan Hsu
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Publication number: 20180012971Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.Type: ApplicationFiled: August 15, 2017Publication date: January 11, 2018Inventors: YI CHUEN ENG, Teng-Chuan Hu, I-Chang Wang, Wei-Chih Chen, Hsiu-Kuan Hsu
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Publication number: 20170352736Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.Type: ApplicationFiled: August 21, 2017Publication date: December 7, 2017Inventors: YI CHUEN ENG, Teng-Chuan Hu, I-Chang Wang, Wei-Chih Chen, Hsiu-Kuan Hsu
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Patent number: 9825039Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor body, a first doped region, a second doped region, a gate and a dielectric layer. The semiconductor body is disposed on a dielectric substrate and has a protrusion portion, a first portion and a second portion. The first portion and the second portion are respectively disposed at two opposite sides of the protrusion portion. The first doped region is disposed in a top of the protrusion portion. The second doped region is disposed in an end of the first portion far away from the protrusion portion. The gate is disposed on the first portion and adjacent to the protrusion portion. The dielectric layer is disposed between the gate and the protrusion portion, and between the gate and the first portion.Type: GrantFiled: October 18, 2016Date of Patent: November 21, 2017Assignee: United Microelectronics Corp.Inventors: Po-Hsieh Lin, Yi-Chuen Eng, Szu-Hao Lai, Ming-Chih Chen
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Publication number: 20170309708Abstract: A field effect transistor is provided in the present invention with an active area including a source region, a drain region, and a channel region. The width of the channel region is larger than the width of the source/drain regions, and at least one of the source region and the drain region is comb-shaped.Type: ApplicationFiled: June 1, 2016Publication date: October 26, 2017Inventors: YI CHUEN ENG, Teng-Chuan Hu, I-Chang Wang, Wei-Chih Chen, Ming-Chih Chen
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Patent number: 9773880Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.Type: GrantFiled: October 7, 2015Date of Patent: September 26, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi Chuen Eng, Teng-Chuan Hu, I-Chang Wang, Wei-Chih Chen, Hsiu-Kuan Hsu
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Publication number: 20170069730Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.Type: ApplicationFiled: October 7, 2015Publication date: March 9, 2017Inventors: YI CHUEN ENG, Teng-Chuan Hu, I-Chang Wang, Wei-Chih Chen, Hsiu-Kuan Hsu
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Patent number: 9343531Abstract: A field effect transistor includes a substrate, an isolation layer, a gate, a channel, drain and a source. The substrate has an active region having a rectangular area and at least one protrusion protruded from the rectangular area. The isolation layer is formed on the substrate and encircling the active region. The gate crosses the active region and is formed above a middle portion of the active region. The channel is formed in the active region directly under the gate, extends to the at least one protrusion, and divides the active region into a first section and a second section. The drain formed in the first section and the source formed in the second section.Type: GrantFiled: August 11, 2014Date of Patent: May 17, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventor: Yi Chuen Eng
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Publication number: 20160013272Abstract: A field effect transistor includes a substrate, an isolation layer, a gate, a channel, drain and a source. The substrate has an active region having a rectangular area and at least one protrusion protruded from the rectangular area. The isolation layer is formed on the substrate and encircling the active region. The gate crosses the active region and is formed above a middle portion of the active region. The channel is formed in the active region directly under the gate, extends to the at least one protrusion, and divides the active region into a first section and a second section. The drain formed in the first section and the source formed in the second section.Type: ApplicationFiled: August 11, 2014Publication date: January 14, 2016Inventor: YI CHUEN ENG
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Patent number: 8269278Abstract: The semiconductor device with a ?-shaped semiconductor conductive layer manufactured by the manufacturing method thereof utilizes two pathways of the ?-shaped semiconductor conductive layer connected to the silicon layer of a silicon-on-insulator (SOI) substrate for heat dissipation, so as to reduce the self-heating effects (SHEs). Furthermore, the semiconductor device of the invention utilizes the self-aligned technique to form a self-aligned structure with a gate unit and the silicon layer, so that the process is simple, the production cost is reduced, the compacted ability and the yield are improved, the off current and short-channel effects (SCEs) are still similar to a conventional UTSOI MOSFET, and the stability and the reliability are therefore superior.Type: GrantFiled: May 7, 2009Date of Patent: September 18, 2012Assignee: National Sun Yat-Sen UniversityInventors: Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin
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Publication number: 20100117151Abstract: The semiconductor device with a ?-shaped semiconductor conductive layer manufactured by the manufacturing method thereof utilizes two pathways of the ?-shaped semiconductor conductive layer connected to the silicon layer of a silicon-on-insulator (SOI) substrate for heat dissipation, so as to reduce the self-heating effects (SHEs). Furthermore, the semiconductor device of the invention utilizes the self-aligned technique to form a self-aligned structure with a gate unit and the silicon layer, so that the process is simple, the production cost is reduced, the compacted ability and the yield are improved, the off current and short-channel effects (SCEs) are still similar to a conventional UTSOI MOSFET, and the stability and the reliability are therefore superior.Type: ApplicationFiled: May 7, 2009Publication date: May 13, 2010Applicant: NATIONAL SUN YAT-SEN UNIVERSITYInventors: Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin