Patents by Inventor Yi-Chuin Tsai
Yi-Chuin Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11931187Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.Type: GrantFiled: March 16, 2018Date of Patent: March 19, 2024Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung UniversityInventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
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Publication number: 20220139826Abstract: A method of generating a power network layout is provided. A first conductive line, generated by a processor, is in a first conductive layer along a first direction. A plurality of second conductive lines, generated by a processor, is in a second conductive layer along a second direction, substantially vertical to the first direction. The second conductive lines overlap with the first conductive line. A first plurality of interlayer vias, generated by a processor, is interposed between the first conductive layer and the second conductive layer at where the second conductive lines overlapping the first conductive line. Each of the second conductive lines has a width such that a first routing track adjacent to the first conductive line is available for routing or a second routing track adjacent to one of the plurality of second conductive lines is available for routing.Type: ApplicationFiled: January 13, 2022Publication date: May 5, 2022Inventors: CHIEN-JU CHAO, FANG-YU FAN, YI-CHUIN TSAI, KUO-NAN YANG, CHUNG-HSING WANG
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Patent number: 11239154Abstract: In some embodiments, a fishbone structure in a power network includes a first conductive segment in a first conductive layer running in a first direction, a plurality of second conductive segments in a second conductive layer running in a second direction and a plurality of interlayer vias between the first conductive layer and the second conductive layer. The second direction is substantially vertical to the first direction. The plurality of second conductive segments overlap with the first conductive segment. The plurality of interlayer vias are formed at where the plurality of second conductive segments overlap with the first conductive segment. Each of the plurality of second conductive segments has a width such that the first conductive segment has a first unit spacing with a first adjacent conductive line or one of the plurality of second conductive segments has a second unit spacing with a second adjacent conductive line.Type: GrantFiled: January 20, 2015Date of Patent: February 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chien-Ju Chao, Fang-Yu Fan, Yi-Chuin Tsai, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 11152348Abstract: An integrated circuit structure includes: a first plurality of cell rows extending in a first direction, each of which has a first row height and comprises a plurality of first cells disposed therein; and a second plurality of cell rows extending in the first direction, each of which has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction, and wherein the plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction.Type: GrantFiled: November 20, 2018Date of Patent: October 19, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kam-Tou Sio, Jiann-Tyng Tzeng, Jack Liu, Yi-Chuin Tsai, Shang-Wei Fang, Sing-Kai Huang, Charles Chew-Yuen Young
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Patent number: 10643986Abstract: A device comprises a first interconnect structure over a first active device layer, a first power circuit in the first active device layer, a second active device layer over and in contact with the first interconnect structure, a first switch in the second active device layer, a second interconnect structure over and in contact with the second active device layer, a third active device layer over and in contact with the second interconnect structure, a second power circuit in the third active device layer and a third interconnect structure over and in contact with the third active device layer and connected to a power source, wherein the power source is configured to provide power to the first power circuit through the first switch.Type: GrantFiled: September 10, 2018Date of Patent: May 5, 2020Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Publication number: 20190164949Abstract: An integrated circuit structure includes: a first plurality of cell rows extending in a first direction, each of which has a first row height and comprises a plurality of first cells disposed therein; and a second plurality of cell rows extending in the first direction, each of which has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction, and wherein the plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction.Type: ApplicationFiled: November 20, 2018Publication date: May 30, 2019Inventors: Kam-Tou SIO, Jiann-Tyng Tzeng, Jack Liu, Yi-Chuin Tsai, Shang-Wei Fang, Sing-Kai Huang
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Publication number: 20190006346Abstract: A device comprises a first interconnect structure over a first active device layer, a first power circuit in the first active device layer, a second active device layer over and in contact with the first interconnect structure, a first switch in the second active device layer, a second interconnect structure over and in contact with the second active device layer, a third active device layer over and in contact with the second interconnect structure, a second power circuit in the third active device layer and a third interconnect structure over and in contact with the third active device layer and connected to a power source, wherein the power source is configured to provide power to the first power circuit through the first switch.Type: ApplicationFiled: September 10, 2018Publication date: January 3, 2019Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 10074641Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.Type: GrantFiled: October 23, 2017Date of Patent: September 11, 2018Assignee: Taiwan Semicondcutor Manufacturing CompanyInventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9984192Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.Type: GrantFiled: February 15, 2016Date of Patent: May 29, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
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Publication number: 20180047716Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.Type: ApplicationFiled: October 23, 2017Publication date: February 15, 2018Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9799639Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.Type: GrantFiled: March 15, 2016Date of Patent: October 24, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9501602Abstract: In some embodiments, in a method, placement of a design layout is performed. The design layout includes a power rail segment, several upper-level power lines and several cells. The upper-level power lines cross over and bound the power rail segment at where the upper-level power lines intersect with the power rail segment. The cells are powered through the power rail segment. For each cell, a respective current through the power rail segment during a respective SW of the cell is obtained. One or more groups of cells with overlapped SWs are determined. One or more EM usages of the power rail segment by the one or more groups of cells using the respective currents of each group of cells are obtained. The design layout is adjusted when any of the one or more EM usages of the power rail segment causes an EM susceptibility of the power rail segment.Type: GrantFiled: April 17, 2014Date of Patent: November 22, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Nitesh Katta, Jerry Chang-Jui Kao, Chin-Shen Lin, Yi-Chuin Tsai, Chou-Kun Lin, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9405883Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.Type: GrantFiled: September 17, 2015Date of Patent: August 2, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Shen Lin, Jerry Chang-Jui Kao, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai, Chi-Yeh Yu, Kuo-Nan Yang
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Publication number: 20160211212Abstract: In some embodiments, a fishbone structure in a power network includes a first conductive segment in a first conductive layer running in a first direction, a plurality of second conductive segments in a second conductive layer running in a second direction and a plurality of interlayer vias between the first conductive layer and the second conductive layer. The second direction is substantially vertical to the first direction. The plurality of second conductive segments overlap with the first conductive segment. The plurality of interlayer vias are formed at where the plurality of second conductive segments overlap with the first conductive segment. Each of the plurality of second conductive segments has a width such that the first conductive segment has a first unit spacing with a first adjacent conductive line or one of the plurality of second conductive segments has a second unit spacing with a second adjacent conductive line.Type: ApplicationFiled: January 20, 2015Publication date: July 21, 2016Inventors: CHIEN-JU CHAO, FANG-YU FAN, YI-CHUIN TSAI, KUO-NAN YANG, CHUNG-HSING WANG
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Publication number: 20160197068Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.Type: ApplicationFiled: March 15, 2016Publication date: July 7, 2016Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9367660Abstract: In some embodiments, in a method, cell layouts of a plurality of cells are received. For each cell, a respective constraint that affects a geometry of an interconnect to be coupled to an output pin of the cell in a design layout is determined based on a geometry of the output pin of the cell in the cell layout.Type: GrantFiled: March 18, 2014Date of Patent: June 14, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Nitesh Katta, Jerry Chang-Jui Kao, Chin-Shen Lin, Yi-Chuin Tsai, Chien-Ju Chao, Kuo-Nan Yang, Chung-Hsing Wang
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Publication number: 20160162619Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.Type: ApplicationFiled: February 15, 2016Publication date: June 9, 2016Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
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Patent number: 9287257Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.Type: GrantFiled: August 27, 2014Date of Patent: March 15, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9262573Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.Type: GrantFiled: March 8, 2013Date of Patent: February 16, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
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Publication number: 20160004809Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.Type: ApplicationFiled: September 17, 2015Publication date: January 7, 2016Inventors: Chin-Shen LIN, Jerry Chang-Jui KAO, Nitesh KATTA, Chou-Kun LIN, Yi-Chuin TSAI, Chi-Yeh YU, Kuo-Nan YANG