Abstract: Methods, systems and apparatus including computer-readable mediums for partially erasing blocks in a memory system to increase reliability are provided. In one aspect, a memory system includes a memory having a plurality of blocks and a memory controller coupled to the memory. The memory controller is configured to: execute a first erase operation on a particular block in the memory, the particular block including multiple sub-blocks each having respective memory cells, one or more memory cells in the particular block being in one or more programmed states before the first erase operation, then execute a second erase operation on a first sub-block of the particular block such that first respective memory cells of the first sub-block are in an erased state after the second erase operation. The memory controller can be configured to not execute the second erase operation on the one or more other sub-blocks of the particular block.

Abstract: A memory device and an access method applied to the memory device are provided. The memory device is electrically connected to a host, and the memory device includes a memory circuit and a memory controller. The memory circuit includes a first memory array and a second memory array. The first memory array and the second memory array respectively provide a first physical space and a second physical space. The memory controller receives an access command from the host. The memory controller performs the access command to the first physical space when the access command is a first type of command, and the memory controller performs the access command to the second physical space when the access command is a second type of command.

Abstract: Methods, systems and apparatus including computer-readable mediums for partially erasing blocks in a memory system to increase reliability are provided. In one aspect, a memory system includes a memory having a plurality of blocks and a memory controller coupled to the memory. The memory controller is configured to: execute a first erase operation on a particular block in the memory, the particular block including multiple sub-blocks each having respective memory cells, one or more memory cells in the particular block being in one or more programmed states before the first erase operation, then execute a second erase operation on a first sub-block of the particular block such that first respective memory cells of the first sub-block are in an erased state after the second erase operation. The memory controller can be configured to not execute the second erase operation on the one or more other sub-blocks of the particular block.

Abstract: A substrate structure with high reflectance includes a base material, a patterned circuit layer, an insulating layer and a metal reflecting layer. The base material includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The insulating layer covers the patterned circuit layer and a part of the first surface exposed by the patterned circuit layer. The metal reflecting layer covers the insulating layer, and a reflectance of the metal reflecting layer is substantially greater than or equal to 85%. A manufacturing method of a substrate structure with high reflectance is also provided.

Abstract: A substrate structure with high reflectance includes a base material, a patterned circuit layer, an insulating layer and a metal reflecting layer. The base material includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The insulating layer covers the patterned circuit layer and a part of the first surface exposed by the patterned circuit layer. The metal reflecting layer covers the insulating layer, and a reflectance of the metal reflecting layer is substantially greater than or equal to 85%. A manufacturing method of a substrate structure with high reflectance is also provided.

Abstract: A memory device includes a memory cell array and a memory controller. The memory cell array includes a plurality of memory blocks. Each of the memory blocks includes a plurality of word lines. A plurality of memory chunks is coupled to at least one of the word lines. The memory controller is configured to program data to a particular memory chunk of the plurality of memory chunks by performing a chunk operation that includes selecting a particular word line from the plurality of word lines, selecting a particular memory chunk from the plurality of memory chunks that are coupled to the particular word line, and applying a program voltage to a particular memory block corresponding to the particular memory chunk to program data to the particular memory chunk.

Abstract: A substrate structure with high reflectance includes a base material, a patterned circuit layer, an insulating layer and a metal reflecting layer. The base material includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The insulating layer covers the patterned circuit layer and a part of the first surface exposed by the patterned circuit layer. The metal reflecting layer covers the insulating layer, and a reflectance of the metal reflecting layer is substantially greater than or equal to 85%. A manufacturing method of a substrate structure with high reflectance is also provided.

Abstract: A memory system, a controller, a memory and a reading method thereof are provided. The reading method includes the following steps. A plurality of duplicated contents which are formed by duplicating one data content several times are received by a voting circuit. A voting procedure is performed by the voting circuit to obtain a voted content which is a majority of the duplicated contents.

Abstract: A substrate structure with high reflectance includes a base material, a patterned circuit layer, an insulating layer and a metal reflecting layer. The base material includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The insulating layer covers the patterned circuit layer and a part of the first surface exposed by the patterned circuit layer. The metal reflecting layer covers the insulating layer, and a reflectance of the metal reflecting layer is substantially greater than or equal to 85%. A manufacturing method of a substrate structure with high reflectance is also provided.

Abstract: A memory system, a controller, a memory and a reading method thereof are provided. The reading method includes the following steps. A plurality of duplicated contents which are formed by duplicating one data content several times are received by a voting circuit. A voting procedure is performed by the voting circuit to obtain a voted content which is a majority of the duplicated contents.

Abstract: A method for manufacturing a quantum dot and a quantum dot are provided. The method includes adding a core semiconductor precursor solution into a seed composition solution. The seed composition solution includes a seed composition, and the seed composition is a dendrimer-metal nanoparticle composite. The core semiconductor precursor solution includes a first semiconductor ion and a second semiconductor ion. The method also includes carrying out a first synthesis reaction to form a core semiconductor material wrapping the seed composition. The core semiconductor material is formed by combining the first semiconductor ion with the second semiconductor ion.

Abstract: An embedded system includes a program to be executed. The program is divided into overlays. The embedded system includes a processor configured to request one of the overlays. The requested overlay includes a segment of the program to be executed by the processor. The embedded system also includes a first level memory device coupled to the processor. The first level memory device stores less than all of the overlays of the program. The embedded system further includes a memory management unit coupled to the processor and the first level memory device. The memory management unit is configured to determine, based on a logical address provided by the processor, whether the requested overlay is stored in the first level memory device. The memory management unit is additionally configured to convert the logical address to a physical address when the requested overlay is stored in the first level memory device. The physical address points to the requested overlay.

Abstract: A controlling method, a channel operating circuit and a memory system for executing a plurality of memory dies with single channel are provided. The plurality of memory dies correspond to a plurality of queue sections of a command queue. The controlling method comprises the following steps: A selecting unit selects one of the plurality of queue sections corresponding one of the plurality of memory dies which is riot at a busy state. An executing unit executes a command stored in one of the plurality of queue sections which is selected.

Abstract: A package structure for a backlight module includes a flexible base film, a plurality of pads, a light-emitting component, a patterned circuit layer. The flexible base film includes a plurality of conductive vias, a first surface, and a second surface opposite to the first surface. The conductive vias connect the first surface and the second surface. In addition, a material of the flexible base film includes polyimide and white fillings. The pads are disposed on the first surface. The conductive vias are connected to the pads. The light-emitting component is disposed on the pads and electrically connected to the pads. The patterned circuit layer is disposed on the second surface and electrically connected to the conductive vias.

Abstract: The present disclosure provides an enhanced wavelength converting structure. The enhanced wavelength converting structure includes a first crosslinked cholesteric liquid crystal layer and a plurality of first quantum dots dispersed in the first crosslinked cholesteric liquid crystal layer. When a first light is incident into the enhanced wavelength converting structure, the plurality of first quantum dots are excited and emit a second light of a wavelength different from a wavelength of the first light, and the second light is toned up via multiple reflections in the first crosslinked cholesteric liquid crystal layer. The present disclosure further provides a luminescent film and a display backlighting unit.

Abstract: A package structure for a backlight module includes a flexible base film, a plurality of pads, a light-emitting component, a patterned circuit layer. The flexible base film includes a plurality of conductive vias, a first surface, and a second surface opposite to the first surface. The conductive vias connect the first surface and the second surface. In addition, a material of the flexible base film includes polyimide and white fillings. The pads are disposed on the first surface. The conductive vias are connected to the pads. The light-emitting component is disposed on the pads and electrically connected to the pads. The patterned circuit layer is disposed on the second surface and electrically connected to the conductive vias.

Abstract: A request is received to access physical information of a memory unit included in a memory device. A determination is made whether the physical information is available in a physical information table present in a memory cache. If the physical information of the memory unit is available in the table, the physical information is accessed from the table. If the physical information is not available in the table, a global directory in the memory cache is accessed, which indicates locations in a non-volatile memory that store the total number of the physical information blocks. From the global directory, a particular location in the non-volatile memory storing a particular physical information block that includes the physical information of the memory unit is determined. The particular physical information block is loaded into the table and the physical information of the memory unit is accessed from the particular physical information block.

Abstract: Systems, methods, and apparatus including computer-readable mediums for managing data arrangement in a super block in a memory such as NAND flash memory are provided. In one aspect, a memory controller includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to determine one or more characteristics of data to be written, allocate a super page of a super block based on the determined characteristics of the data and block information of the physical blocks of the planes, the super block combining one or more physical blocks from the planes, the super page combining one or more single pages from the corresponding one or more physical blocks in the super block, arrange the data to the one or more single pages in the super page, and program the super page to write the data in the one or more single pages.

Abstract: A package structure for a display includes a flexible base film, a plurality of pads, a light-emitting component array, and a patterned circuit layer. The flexible base film includes a plurality of conductive vias, a first surface, and a second surface opposite to the first surface. The conductive vias connect the first surface and the second surface. A material of the flexible base film includes polyimide and black fillings. The pads are disposed on the first surface. The conductive vias are connected to the pads. The light-emitting component array includes a plurality of light-emitting component sets disposed on the pads and electrically connected to the pads. Each light-emitting component set includes a plurality of light-emitting components having different colors. The patterned circuit layer is disposed on the second surface and electrically connected to the conductive vias.

Abstract: A portable toy gun capable of being quickly assembled and dismantled, including a first gun barrel and a second gun barrel, a gun stock mounted at one end of the first gun barrel, a trigger component connected to one side of the first gun barrel, and a handle and a magazine mounted at two opposite ends of the trigger component respectively. The first gun barrel includes an outer sleeve, a first bore, and a locking mechanism mounted on the outer side of one end of the outer sleeve. A plug is mounted at one end of the first bore, and a guiding locating protrusion is disposed on one side of the plug. The second gun barrel includes a second outer sleeve and a second bore. One end of the second outer sleeve defines a locking hole corresponding to the locking mechanism and a slot corresponding to the plug.