Abstract: A manufacturing method of a semiconductor device at least includes the following steps. A substrate having a stacked structure is provided. An epitaxy process is performed to form an epitaxial layer on the substrate on two sides of the stacked structure. A recess is forming on the two sides of the stacked structure, wherein the recess penetrates through the epitaxial layer, extends into the substrate, and has a tip located in the substrate. A source/drain region is formed in the recess, wherein a material of the source/drain region comprises silicon germanium. A spacer wall material layer is formed on the substrate. A portion of the stacked structure is removed to from a gate structure. A portion of the spacer wall material layer is removed to form a spacer wall on the epitaxial layer. A semiconductor device is also provided.

Abstract: A semiconductor package including a chip stack structure, a redistribution layer (RDL) structure and conductive plugs is provided. The chip stack structure includes stacked chips. Each of the chips includes a pad. The pads on the chips are located on the same side of the chip stack structure. The RDL structure is disposed on the first sidewall of the chip stack structure and adjacent to the pads. The conductive plugs penetrate through the RDL structure. The conductive plug is connected to the corresponding pad.

Abstract: A semiconductor package including a chip stack structure, a redistribution layer (RDL) structure and conductive plugs is provided. The chip stack structure includes stacked chips. Each of the chips includes a pad. The pads on the chips are located on the same side of the chip stack structure. The RDL structure is disposed on the first sidewall of the chip stack structure and adjacent to the pads. The conductive plugs penetrate through the RDL structure. The conductive plug is connected to the corresponding pad.

Abstract: A static random access memory including at least one memory cell is provided. The memory cell includes a first inverter, a second inverter, a first pass gate transistor, a second pass gate transistor, a first non-volatile memory, and a second non-volatile memory. The first inverter and the second inverter are coupled to each other. The first pass gate transistor is coupled between the first inverter and the first bit line. The second pass gate transistor is coupled between the second inverter and the second bit line. The first non-volatile memory is coupled between the first pass gate transistor and the first bit line. The second non-volatile memory is coupled between the second pass gate transistor and the second bit line.

Abstract: A manufacturing method of a semiconductor device at least includes the following steps. A substrate having a stacked structure is provided. An epitaxy process is performed to form an epitaxial layer on the substrate on two sides of the stacked structure. A recess is forming on the two sides of the stacked structure, wherein the recess penetrates through the epitaxial layer, extends into the substrate, and has a tip located in the substrate. A source/drain region is formed in the recess, wherein a material of the source/drain region comprises silicon germanium. A spacer wall material layer is formed on the substrate. A portion of the stacked structure is removed to from a gate structure. A portion of the spacer wall material layer is removed to form a spacer wall on the epitaxial layer. A semiconductor device is also provided.

Abstract: A semiconductor device including a substrate, a gate structure, a source/drain region, an epitaxial layer, and a spacer wall is provided. The substrate has an upper surface. The gate structure is arranged on the upper surface. The source/drain region is arranged on two sides of the gate structure, is partially embedded in the substrate, and has a tip located in the substrate. A material of the source/drain region includes silicon germanium. The epitaxial layer is arranged between the gate structure and the source/drain region. The spacer wall is arranged on the epitaxial layer on the two sides of the gate structure. A manufacturing method of a semiconductor device is also provided.

Abstract: A semiconductor device including a substrate, a gate structure, a source/drain region, an epitaxial layer, and a spacer wall is provided. The substrate has an upper surface. The gate structure is arranged on the upper surface. The source/drain region is arranged on two sides of the gate structure, is partially embedded in the substrate, and has a tip located in the substrate. A material of the source/drain region includes silicon germanium. The epitaxial layer is arranged between the gate structure and the source/drain region. The spacer wall is arranged on the epitaxial layer on the two sides of the gate structure. A manufacturing method of a semiconductor device is also provided.

Abstract: A static random access memory and the manufacturing method thereof are provided. By forming the specific gate structure(s) to be concave gate structure(s) and by adjusting the ratio of the effective channel width for these gate structures, the performance of the static random access memory is enhanced.

Abstract: A static random access memory and the manufacturing method thereof are provided. By forming the specific gate structure(s) to be concave gate structure(s) and by adjusting the ratio of the effective channel width for these gate structures, the performance of the static random access memory is enhanced.