Abstract: A liquid crystal display having common voltage compensation mechanism includes a liquid-crystal capacitor common electrode for receiving a liquid-crystal capacitor common voltage, a storage capacitor common electrode for receiving a storage capacitor common voltage, a common voltage generator for providing the liquid-crystal capacitor common voltage according to a preliminary common voltage, a common voltage compensation circuit electrically connected to the liquid-crystal capacitor common electrode and the storage capacitor common electrode, and a timing controller electrically connected to the common voltage compensation circuit. The common voltage compensation circuit is utilized for generating the storage capacitor common voltage through performing a ripple inverting operation according to the liquid-crystal capacitor common voltage, the preliminary common voltage and a compensation control signal.

Abstract: A liquid crystal display having common voltage compensation mechanism includes a liquid-crystal capacitor common electrode for receiving a liquid-crystal capacitor common voltage, a storage capacitor common electrode for receiving a storage capacitor common voltage, a common voltage generator for providing the liquid-crystal capacitor common voltage according to a preliminary common voltage, a common voltage compensation circuit electrically connected to the liquid-crystal capacitor common electrode and the storage capacitor common electrode, and a timing controller electrically connected to the common voltage compensation circuit. The common voltage compensation circuit is utilized for generating the storage capacitor common voltage through performing a ripple inverting operation according to the liquid-crystal capacitor common voltage, the preliminary common voltage and a compensation control signal.

Abstract: A plurality of pixels of a display panel are driven with a first polarity inversion to display a first image, driven with the first polarity inversion to display a second image after the first image is displayed, driven with a second polarity inversion to display a third image, and driven with the second polarity inversion to display a fourth image after the third image is displayed. The polarity of a first pixel of the first image is opposite to the polarity of a first pixel of the second image. The polarity of a first pixel of the third image is opposite to the polarity of a first pixel of the fourth image. The first polarity inversion is different from the second polarity inversion.

Abstract: The present invention discloses a method and system for detecting the frame boundary of a data stream received in Forward Error Correction layer in the Ethernet. The present invention can increase the speed of frame boundary detection and the speed of frame synchronization without adding any overheads of hardware.

Abstract: An exemplary control method of an output signal (e.g., from a timing controller in a flat panel display device) is adapted to be operative with a first signal with multiple pulses. In the control method, during a first time segment including part of the pulses of the first signal, a first enable signal is provided passing through a transmission path after a first time length from a rising edge of each of the part of the pulses. During a second time segment including another part of the pulses of the first signal, a second enable signal is provided passing through a part of the transmission path after a second time length from a rising edge of each of the another part of the pulses. The first time length is shorter than the second time length.

Abstract: The present invention discloses a frame boundary detection system and a synchronization system for a data stream received by an Ethernet Forward Error Correction layer. The frame boundary detection system includes a shifter, two descramblers, a syndrome generator and trapper. The error trapper includes a big-little endian mode controller for controlling the big-little endian conversion of the error trapper. If the error trapper operates in the big endian mode, the error trapper implements the function of the syndrome generator, operates at the same time with the syndrome generator, and performs a second FEC check, wherein when the shifter performs the FEC check by intercepting data with a length of one frame plus A bits, two start positions of the frame can be verified, where A is a positive integer less than a length of one frame. The invention can improve the frame boundary detection speed and the frame synchronization speed, and increase only a few hardware overheads.

Abstract: A display apparatus includes a panel module and a backlight module. The backlight module is disposed under the panel module. The backlight module includes a frame, a light guide plate, and a reflector. The frame supports the edge of the light guide plate. The reflector is disposed at the bottom of the light guide plate. The edge of the reflector and the edge of the frame horizontally form an engaging seam without overlapping, and the engaging seam is substantially in a serrated shape.

Abstract: A liquid crystal display having common voltage compensation mechanism includes a liquid-crystal capacitor common electrode for receiving a liquid-crystal capacitor common voltage, a storage capacitor common electrode for receiving a storage capacitor common voltage, a common voltage generator for providing the liquid-crystal capacitor common voltage according to a preliminary common voltage, a common voltage compensation circuit electrically connected to the liquid-crystal capacitor common electrode and the storage capacitor common electrode, and a timing controller electrically connected to the common voltage compensation circuit. The common voltage compensation circuit is utilized for generating the storage capacitor common voltage through performing a ripple inverting operation according to the liquid-crystal capacitor common voltage, the preliminary common voltage and a compensation control signal.

Abstract: A display apparatus includes a panel module and a backlight module. The backlight module is disposed under the panel module. The backlight module includes a frame, a light guide plate, and a reflector. The frame supports the edge of the light guide plate. The reflector is disposed at the bottom of the light guide plate. The edge of the reflector and that of the frame horizontally form an engaging seam without overlapping, and the engaging seam is substantially in a serrated shape.

Abstract: Disclosed are a method and apparatus for detecting frame boundary for a data stream received at an Ethernet FEC layer, as well as a decoding method and system for the same. The apparatus for detecting frame boundary may comprise: a buffer for buffering data in a data stream, a length of the data in the buffer being greater than one frame; a syndrome generator for calculating a current syndrome based on a first data item, a second data item, and an intermediate calculation result of a previous syndrome, wherein the first data item is the last bit in a current candidate frame, and the second data item is a bit preceding the current candidate frame; and a comparator for using the current syndrome to check whether the bit preceding the current candidate frame is a frame boundary of an Ethernet FEC layer. The apparatus for detecting frame boundary can improve the speed of frame boundary detection.

Abstract: A method and apparatus for constructing a clock tree for an integrated circuit design is disclosed, the method comprising: extracting the path delays between the sequential devices in a placed netlist by performing timing analysis on the placed netlist; and constructing a clock tree for driving the sequential devices according to the path delays between the sequential devices so as to make the sum of the products of the timing delay between any two sequential devices and a clock tree branch weight of the two sequential devices minimum, wherein the clock tree branch weight of the two sequential devices is positively correlated with the number of clock tree levels from the branch point of the clock tree relative to the two sequential devices to the two sequential devices.

Abstract: An exemplary gate output control method includes the following steps: providing a gate control signal; using an angling control signal to angling modulate the gate control signal so as to generate a modulated gate control signal; and supplying the modulated gate control signal to a first integrated gate driver circuit and a second integrated gate driver circuit, to sequentially control the gate outputs of the first integrated gate driver circuit and the second integrated gate driver circuit. A duty ratio used by the angling control signal at the time of modulating the gate control signal to generate the modulated gate control signal for the first integrated gate driver circuit is different from another duty ratio used by the angling control signal at the time of modulating the gate control signal to generate the modulated gate control signal for the second integrated gate driver circuit.

Abstract: A display apparatus includes a panel module and a backlight module. The backlight module is disposed under the panel module. The backlight module includes a frame, a light guide plate, and a reflector. The frame supports the edge of the light guide plate. The reflector is disposed at the bottom of the light guide plate. The edge of the reflector and that of the frame horizontally form an engaging seam without overlapping, and the engaging seam is substantially in a serrated shape.

Abstract: A display apparatus includes a panel module and a backlight module. The backlight module is disposed under the panel module. The backlight module includes a frame, a light guide plate, and a reflector. The frame supports the edge of the light guide plate. The reflector is disposed at the bottom of the light guide plate. The edge of the reflector and the edge of the frame horizontally form an engaging seam without overlapping, and the engaging seam is substantially in a serrated shape.

Abstract: A liquid crystal display having common voltage compensation mechanism includes a liquid-crystal capacitor common electrode for receiving a liquid-crystal capacitor common voltage, a storage capacitor common electrode for receiving a storage capacitor common voltage, a common voltage generator for providing the liquid-crystal capacitor common voltage according to a preliminary common voltage, a common voltage compensation circuit electrically connected to the liquid-crystal capacitor common electrode and the storage capacitor common electrode, and a timing controller electrically connected to the common voltage compensation circuit. The common voltage compensation circuit is utilized for generating the storage capacitor common voltage through performing a ripple inverting operation according to the liquid-crystal capacitor common voltage, the preliminary common voltage and a compensation control signal.

Abstract: An exemplary control method of an output signal (e.g., from a timing controller in a flat panel display device) is adapted to be operative with a first signal with multiple pulses. In the control method, during a first time segment including part of the pulses of the first signal, a first enable signal is provided passing through a transmission path after a first time length from a rising edge of each of the part of the pulses. During a second time segment including another part of the pulses of the first signal, a second enable signal is provided passing through a part of the transmission path after a second time length from a rising edge of each of the another part of the pulses. The first time length is shorter than the second time length.

Abstract: The present invention discloses a method and system for detecting the frame boundary of a data stream received in Forward Error Correction layer in the Ethernet. The present invention can increase the speed of frame boundary detection and the speed of frame synchronization without adding any overheads of hardware.

Abstract: A method and apparatus for constructing a clock tree for an integrated circuit design is disclosed, the method comprising: extracting the path delays between the sequential devices in a placed netlist by performing timing analysis on the placed netlist; and constructing a clock tree for driving the sequential devices according to the path delays between the sequential devices so as to make the sum of the products of the timing delay between any two sequential devices and a clock tree branch weight of the two sequential devices minimum, wherein the clock tree branch weight of the two sequential devices is positively correlated with the number of clock tree levels from the branch point of the clock tree relative to the two sequential devices to the two sequential devices.

Abstract: Disclosed are a method and apparatus for detecting frame boundary for a data stream received at an Ethernet FEC layer, as well as a decoding method and system for the same. The apparatus for detecting frame boundary may comprise: a buffer for buffering data in a data stream, a length of the data in the buffer being greater than one frame; a syndrome generator for calculating a current syndrome based on a first data item, a second data item, and an intermediate calculation result of a previous syndrome, wherein the first data item is the last bit in a current candidate frame, and the second data item is a bit preceding the current candidate frame; and a comparator for using the current syndrome to check whether the bit preceding the current candidate frame is a frame boundary of an Ethernet FEC layer. The apparatus for detecting frame boundary can improve the speed of frame boundary detection.

Abstract: A display device includes multiple first data lines, multiple second data lines, multiple pixel columns, at least a first charge sharing switch circuit and at least a second charge sharing switch circuit. The second data lines are alternately arranged with the first data lines. Each of the pixel columns includes multiple first pixels and multiple second pixels. The first pixels of each of the pixel columns are coupled to one of the first data lines, and the second pixels of each of the pixel columns are coupled to one of the second data lines. The first charge sharing switch circuit each is electrically coupled to at least a part of the first data lines. The second charge sharing switch circuit each is electrically coupled to at least a part of the second data lines. A display device driving method and a source driving circuit also are provided.