Patents by Inventor Yi-Hsing HSIAO

Yi-Hsing HSIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210325338
    Abstract: A biosensor includes a semiconductor layer having a first surface and a second surface opposite to the first surface, a FET device in the semiconductor layer, an isolation layer over the first surface of the semiconductor layer, a dielectric layer over the isolation layer and the first surface of the semiconductor layer, and a pair of first electrodes and a pair of second electrodes over the dielectric layer and separated from each other. The isolation layer has a rectangular opening substantially aligned with the FET device. The rectangular opening has pair of first sides and a pair of second sides. An extending direction of the pair of first sides is perpendicular to an extending direction of the pair of second sides. The pair of first electrodes is disposed over the pair of first sides, and the pair of second electrodes is disposed over the pair of second sides.
    Type: Application
    Filed: April 16, 2020
    Publication date: October 21, 2021
    Inventors: YI-HSING HSIAO, JUI-CHENG HUANG, YU-JIE HUANG
  • Patent number: 11137370
    Abstract: A sensor with a nanowire heater may be provided. The sensor may be patterned in a device layer of a Silicon on Insulation (SOI) wafer comprising a backside layer and a Buried Oxide (BOX) layer and the nanowire heater may be patterned in the device layer of the SOI wafer adjacent to the sensor. Next, metal routing may be created for the SOI wafer and a bond carrier wafer may be provided on a metal routing side of the SOI wafer. The backside layer may then be ground until the BOX layer is exposed. Then the device layer may be patterned through the BOX layer to expose the sensor and the nanowire heater. A dielectric may be deposited covering at least one of the following: the sensor; and the nanowire heater.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Allen Timothy Chang, Tung-Tsun Chen, Jui-Cheng Huang, Yu-Jie Huang, Yi-Hsing Hsiao
  • Publication number: 20200041447
    Abstract: A sensor with a nanowire heater may be provided. The sensor may be patterned in a device layer of a Silicon on Insulation (SOI) wafer comprising a backside layer and a Buried Oxide (BOX) layer and the nanowire heater may be patterned in the device layer of the SOI wafer adjacent to the sensor. Next, metal routing may be created for the SOI wafer and a bond carrier wafer may be provided on a metal routing side of the SOI wafer. The backside layer may then be ground until the BOX layer is exposed. Then the device layer may be patterned through the BOX layer to expose the sensor and the nanowire heater. A dielectric may be deposited covering at least one of the following: the sensor; and the nanowire heater.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 6, 2020
    Inventors: Allen Timothy Chang, Tung-Tsun Chen, Jui-Cheng Huang, Yu-Jie Huang, Yi-Hsing Hsiao
  • Publication number: 20200042057
    Abstract: In an embodiment, a circuit includes: an error amplifier; a temperature sensor, wherein the temperature sensor is coupled to the error amplifier; a discrete time controller coupled to the error amplifier, wherein the discrete time controller comprises digital circuitry; a multiple bits quantizer coupled to the discrete time controller, wherein the multiple bits quantizer produces a digital code output; and a heating array coupled to the multiple bits quantizer, wherein the heating array is configured to generate heat based on the digital code output.
    Type: Application
    Filed: June 14, 2019
    Publication date: February 6, 2020
    Inventors: Jui-Cheng HUANG, Yi-Hsing HSIAO, Yu-Jie HUANG, Tsung-Tsun CHEN, Allen Timothy CHANG
  • Patent number: 10344258
    Abstract: A sorting device is provided. The sorting device includes: a carrier substrate; an input unit disposed on the carrier substrate for inputting a biological sample into the sorting device; a porous material disposed on the carrier substrate and adjacent to the input unit, wherein the porous material contains antigen molecules having specificity to a target biological analyte; a driving module generating at least one driving force in the porous material so as to sort the biological sample based on the affinity for the antigen and the driving force; and an output unit disposed on the carrier substrate and adjacent to the porous material for collecting the sorted target biological analyte. A sorting method is also provided.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 9, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chih-Chen Chen, Yi-Hsing Hsiao
  • Publication number: 20170121665
    Abstract: A sorting device is provided. The sorting device includes: a carrier substrate; an input unit disposed on the carrier substrate for inputting a biological sample into the sorting device; a porous material disposed on the carrier substrate and adjacent to the input unit, wherein the porous material contains antigen molecules having specificity to a target biological analyte; a driving module generating at least one driving force in the porous material so as to sort the biological sample based on the affinity for the antigen and the driving force; and an output unit disposed on the carrier substrate and adjacent to the porous material for collecting the sorted target biological analyte. A sorting method is also provided.
    Type: Application
    Filed: March 25, 2016
    Publication date: May 4, 2017
    Inventors: Chih-Chen CHEN, Yi-Hsing HSIAO