Abstract: A chip chuck includes front and back slopes obliquely extending toward a bottom surface from front and back edges of a top surface having a chip placement area for supporting a chip under test, and is defined with an imaginary vertical reference line perpendicular to the chip placement area and an imaginary horizontal reference line. The front and back slopes are connected with the chip placement area and each provided with an included acute angle with respect to the imaginary horizontal reference line, thereby avoiding interference with light emitted from the chip. A chip supporting device includes a chip chuck, and an optical sensing module fixed relative thereto and including an optical sensor whose light receiving surface faces toward a back light emitting surface of the chip, thereby enabling optical characteristic inspection of front and back light emitting surfaces of the chip at the same time.

Abstract: A communication device comprising: a first unit having a first antenna, a second antenna, and a first signal transmitting and receiving circuitry; a second unit having a third antenna, a fourth antenna, and a second signal transmitting and receiving circuitry, wherein the second unit is located in proximity to the first unit; and wherein the second unit is capable of receiving signals at a first signal frequency, down converting the signals to a second signal frequency, and relaying the signals through a barrier to the first unit. Wherein the first signal frequency is in the millimeter wave range and the second signal frequency is in the microwave range.

Abstract: A semiconductor device includes a substrate, a dielectric layer, a plurality of dielectric patterns and a conductive pad. The substrate includes a first surface and a second surface opposite to the first surface. The dielectric layer is disposed at the first surface of the substrate, and the substrate is disposed between the dielectric layer and the second surface of the substrate. The dielectric patterns are disposed on the dielectric layer and between the first surface and the second surface of the substrate. The conductive pad is inserted between the plurality of dielectric patterns and extended into the dielectric layer.

Abstract: The present disclosure describes systems and techniques directed to optical image stabilization movement to create a super-resolution image of a scene. The systems and techniques include a user device (102) introducing (502), through an optical image stabilization system (114), movement to one or more components of a camera system (112) of the user device (102). The user device (102) then captures (504) respective and multiple frames (306) of an image of a scene, where the respective and multiple frames (306) of the image of the scene have respective, sub-pixel offsets of the image of the scene across the multiple frames (306) as a result of the introduced movement to the one or more components of the camera system (112). The user device (102) performs (506), based on the respective, sub-pixel offsets of the image of the scene across the respective, multiple frames (306), super-resolution computations and creates (508) the super-resolution image of the scene based on the super-resolution computations.

Abstract: A sterilization apparatus for a portable electronic device including a cabinet and a carrier is provided. The carrier includes a base slidably disposed on the cabinet, multiple first positioning elements and multiple second positioning elements disposed in parallel on the base, multiple sterilization light sources corresponding to the second positioning elements and multiple pressure sensors disposed in parallel in the base. The base is configured to carry at least one portable electronic device. One second positioning element is disposed between any two adjacent first positioning elements, and any first positioning element and any second positioning element adjacent to each other are separated by a positioning space. The pressure sensors are respectively located in the positioning spaces. One sterilization light source is disposed between any two adjacent pressure sensors, and the pressure sensors are configured to sense a pressure from the portable electronic device.

Abstract: CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a plurality of dielectric patterns, a first conductive element and a second conductive element. The semiconductor substrate has a pixel region and a circuit region. The dielectric patterns are disposed between the first portion and the second portion, wherein top surfaces of the plurality of dielectric patterns are lower than top surfaces of the first and second portions. The first conductive element is disposed below the plurality of dielectric patterns. The second conductive element inserts between the plurality of dielectric patterns to electrically connect the first conductive element.

Abstract: The present disclosure describes systems and techniques for creating a super-resolution image (122) of a scene captured by a user device (102). Natural handheld motion (110) introduces, across multiple frames (204, 206, 208) of an image of a scene, sub-pixel offsets that enable the use of super-resolution computations (210) to form color planes (212, 214, 216), which are accumulated (218) and combined (220) to create a super-resolution image (122) of the scene.

Abstract: An electronic device including a first body, a second body, a hinge structure, an electronic assembly and a linkage mechanism is provided. The first body and the second body are pivoted to each other through the hinge structure. The electronic assembly is disposed on the first body. The linkage mechanism is disposed in the first body and connected between the hinge structure and the electronic assembly. When the second body is closed to the first body, the electronic assembly is hidden between the first body and the second body. When the second body is opened relative to the first body with an opening angle less than a predetermined angle, the hinge structure does not drive the linkage mechanism. When the second body is opened relative to the first body with the opening angle not less than the predetermined angle, the hinge structure drives the linkage mechanism and the linkage mechanism drives the electronic assembly to be opened relative to the first body.

Abstract: A micro-scale wireless heater includes: a support layer having first and second sides and a cavity formed on the second side; a first electrode plate and a first conduction line disposed on the second side; a second electrode plate and a coil both embedded into a slot on the first side, wherein the support layer is disposed between the first and second electrode plates forming a capacitor, the coil forms an inductor, and the slot communicates with the cavity; and a second conduction line disposed in the cavity. The first and second electrode plates are electrically connected together through the first and second conduction lines and the coil in order. Three exposed surfaces of the second electrode plate, the coil and the first side are flush with one another. The inductor and the capacitor convert an electromagnetic wave into heat. A fabrication method and applications thereof are also provided.

Abstract: An electronic device including a first body, a second body, a hinge structure, an electronic assembly and a linkage mechanism is provided. The first body and the second body are pivoted to each other through the hinge structure. The electronic assembly is disposed on the first body. The linkage mechanism is disposed in the first body and connected between the hinge structure and the electronic assembly. When the second body is closed to the first body, the electronic assembly is hidden between the first body and the second body. When the second body is opened relative to the first body with an opening angle less than a predetermined angle, the hinge structure does not drive the linkage mechanism. When the second body is opened relative to the first body with the opening angle not less than the predetermined angle, the hinge structure drives the linkage mechanism and the linkage mechanism drives the electronic assembly to be opened relative to the first body.

Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.

Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.

Abstract: A micro-scale wireless heater includes: a support layer having first and second sides and a cavity formed on the second side; a first electrode plate and a first conduction line disposed on the second side; a second electrode plate and a coil both embedded into a slot on the first side, wherein the support layer is disposed between the first and second electrode plates forming a capacitor, the coil forms an inductor, and the slot communicates with the cavity; and a second conduction line disposed in the cavity. The first and second electrode plates are electrically connected together through the first and second conduction lines and the coil in order. Three exposed surfaces of the second electrode plate, the coil and the first side are flush with one another. The inductor and the capacitor convert an electromagnetic wave into heat. A fabrication method and applications thereof are also provided.

Abstract: A semiconductor device includes a substrate, a conductive layer, a transparent layer, a transparent hard mask layer, a carrier, and a device layer. The substrate has a first surface and a second surface opposite to each other. The conductive layer is disposed on the first surface of the substrate. The transparent layer is disposed on the conductive layer. The transparent hard mask layer is disposed on the transparent layer, in which the substrate has an etch selectivity with respect to the transparent hard mask layer. The device layer is disposed between the carrier and the second surface of the substrate, in which various portions of the device layer are respectively exposed by various through holes which pass through the transparent hard mask layer, the transparent layer, the conductive layer, and the substrate.

Abstract: A wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die. The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.

Abstract: CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a plurality of dielectric patterns, a first conductive element and a second conductive element. The semiconductor substrate has a pixel region and a circuit region. The dielectric patterns are disposed between the first portion and the second portion, wherein top surfaces of the plurality of dielectric patterns are lower than top surfaces of the first and second portions. The first conductive element is disposed below the plurality of dielectric patterns. The second conductive element inserts between the plurality of dielectric patterns to electrically connect the first conductive element.

Abstract: CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a dielectric layer, an interconnect, a bonding pad and a dummy pattern. The semiconductor substrate has a pixel region and a circuit region. The dielectric layer is surrounded by the semiconductor substrate in the circuit region. The interconnect is disposed over the dielectric layer in the circuit region. The bonding pad is disposed in the dielectric layer and electrically connects the interconnect in the circuit region. The dummy pattern is disposed in the dielectric layer and surrounds the bonding pad in the circuit region.

Abstract: CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a dielectric layer, an interconnect, a bonding pad and a dummy pattern. The semiconductor substrate has a pixel region and a circuit region. The dielectric layer is surrounded by the semiconductor substrate in the circuit region. The interconnect is disposed over the dielectric layer in the circuit region. The bonding pad is disposed in the dielectric layer and electrically connects the interconnect in the circuit region. The dummy pattern is disposed in the dielectric layer and surrounds the bonding pad in the circuit region.

Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.

Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.