Abstract: A semiconductor structure includes a pair of gate structures and an isolation structure. Each of the gate structures includes a work function metal, a gate, and a barrier layer between the work function metal and the gate. The isolation structure is disposed between the gate structures. The barrier layer covers a sidewall of the isolation structure.

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and a single spacer wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The single spacer wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.

Abstract: A video matrix controller, including a receiving module, a matrix switch module and a transmission module. The matrix switch module is coupled between the receiving module and the transmission module. The receiving module includes a first port interface and a first transceiver. The first port interface receives image data and converts it to a signal, and transmits it to the first transceiver. The transmission module includes a second transceiver and a second port interface. The signal is transmitted from the first transceiver to the matrix switch module. The second transceiver receives the signal, and the second port interface converts the signal to image data and transmits it to a corresponding external display device.

Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a semiconductor substrate and forming a dummy shielding layer over the semiconductor substrate and the gate stack. The method also includes forming source and drain features near the gate stack after the dummy shielding layer is formed. The method further includes removing the dummy shielding layer after the source and drain features are formed such that substantially no dummy shielding layer remains on the source and drain features.

Abstract: A process of manufacturing a semiconductor structure is provided. The process begins with forming a work function metal layer on a substrate, and a hardmask is covered over the work function metal layer. A trench is formed to penetrate the hardmask and the work function metal layer, and an isolation structure is filled in the trench.

Abstract: A method for specific linkage to a glycoprotein includes obtaining a glycoprotein having a monoglycan or diglycan attached thereto; producing a reactive functional group on a sugar unit on the glycoprotein; and coupling a linker or a payload to the reactive functional group on the glycoprotein.

Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a semiconductor substrate and forming a dummy shielding layer over the semiconductor substrate and the gate stack. The method also includes forming source and drain features near the gate stack after the dummy shielding layer is formed. The method further includes removing the dummy shielding layer after the source and drain features are formed such that substantially no dummy shielding layer remains on the source and drain features.

Abstract: Mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and a single spacer wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The single spacer wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.

Abstract: A halogen-free resin composition, a copper clad laminate using the same, and a printed circuit board using the same are introduced. The halogen-free resin composition comprising (A) 100 parts by weight of epoxy resin; (B) 3 to 15 parts by weight of diaminodiphenyl sulfone (DDS); and (C) 5 to 70 parts by weight of phenolic co-hardener. The halogen-free resin composition features specific ingredients and proportion to thereby achieve satisfactory maximum preservation period of the prepreg manufactured from the halogen-free resin composition, control the related manufacturing process better, and attain satisfactory laminate properties, such as a high degree of water resistance, a high degree of heat resistance, and satisfactory dielectric properties, and thus is suitable for producing a prepreg or a resin film to thereby be applicable to copper clad laminates and printed circuit boards.

Abstract: A keyboard-video-mouse (KVM) switch and an operating method thereof are disclosed. The KVM switch is coupled between at least one peripheral device and controlled computers. The method includes steps of: determining whether the hot-key mode of KVM switch is started; if yes, when the KVM switch receives a first signal from a specific controlled computer of the controlled computers, directly passing the first signal to a corresponding specific peripheral device of the at least one peripheral device; when the KVM switch receives a second signal in response from the specific peripheral device within a predetermined period of time, determining whether the second signal includes a specific data; if yes, replacing the specific data in the second signal with an irrelevant data to form a third signal and transmitting the third signal to the specific controlled computer. The irrelevant data corresponds to the specific controlled computer and has no effect on the specific controlled computer.

Abstract: In some embodiments, a semiconductor structure includes a substrate, a dielectric region, a non-planar structure and a gate stack. The dielectric region is formed on the substrate, and has a top surface. The non-planar structure protrudes from the top surface, and includes a channel region, and source and drain regions formed on opposite sides of the channel region. The gate stack is formed on the top surface, wraps around the channel region, and includes a gate top surface, and a gate side wall that does not intersect the non-planar structure. The gate side wall has a first distance from a vertical plane at a level of the top surface, and a second distance from the vertical plane at a level of the gate top surface. The vertical plane is vertical with respect to the top surface, and intersects the non-planar structure. The first distance is shorter than the second distance.

Abstract: A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The semiconductor device structure also includes a sealing structure over a sidewall of the gate stack, and a width ratio of the sealing structure to the gate stack is in a range from about 0.05 to about 0.7. The semiconductor device structure further includes an etch stop layer over the semiconductor substrate, the gate stack, and the sealing structure. The etch stop layer is in contact with the sealing structure.

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and an insulating wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The insulating wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.

Abstract: The present disclosure provides a track transmission system and the track transmission device thereof. The track transmission system comprises at least a track transmission device, a connecting device, and a control device. The track transmission device is provided for disposing slidably at least an electronic device. In addition, signal transmission with the control device can be accomplished through the connecting device. The electronic device is coupled to the circuit board of the track transmission device by contacting. As the electronic device slides along the track transmission device, signal transmission with the control device still can be maintained.

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure, the virtual surface is formed between the upper portion and the lower portion, and the lower portion has a tapered width which is gradually tapered from the virtual interface to a bottom surface of the lower portion.

Abstract: A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.