Patents by Inventor Yi-Jou Lin

Yi-Jou Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150346469
    Abstract: A projector includes an image ray generator and a projecting lens, wherein the image ray generator generates image rays. The projecting lens includes a relay optical system for receiving the image rays and a projection optical system having at least one lens and a reflector. Whereby, the image rays pass through the relay optical system, pass through the at least one lens, and then are reflected by the reflector. After being reflected, the image rays pass through the at least one lens again, and then leave the projecting lens to be projected onto a screen. In addition, the invention further discloses the structure of the projecting lens and a method of projecting images.
    Type: Application
    Filed: May 27, 2014
    Publication date: December 3, 2015
    Inventors: Yi-Jou LIN, Hsin-Ying WU
  • Publication number: 20150255447
    Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
    Type: Application
    Filed: May 22, 2015
    Publication date: September 10, 2015
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh
  • Patent number: 9048222
    Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: June 2, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh
  • Patent number: 9040381
    Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Der-Chyang Yeh, Shuo-Mao Chen, Chiung-Han Yeh, Yi-Jou Lin
  • Patent number: 8680647
    Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: March 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Der-Chyang Yeh, Shuo-Mao Chen, Chiung-Han Yeh, Yi-Jou Lin
  • Publication number: 20140073091
    Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.
    Type: Application
    Filed: November 14, 2013
    Publication date: March 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Der-Chyang Yeh, Shuo-Mao Chen, Chiung-Han Yeh, Yi-Jou Lin
  • Publication number: 20130168805
    Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.
    Type: Application
    Filed: May 4, 2012
    Publication date: July 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Der-Chyang Yeh, Shuo-Mao Chen, Chiung-Han Yeh, Yi-Jou Lin