Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: The present invention relates to a support of a computer peripheral device including a first frame, a second frame pivotally coupled to the first frame at a first end, and a movable arm connected to and movable relative to the second frame. The second frame has an extension at the other end for clamping an object between the extension and the first frame. A computer peripheral device is coupled to an end of the movable arm opposite the end that is coupled to the second frame.

Abstract: The present invention relates to a support of a computer peripheral device including a first frame, a second frame pivotally coupled to the first frame at a first end, and a movable arm connected to and movable relative to the second frame. The second frame has an extension at the other end for clamping an object between the extension and the first frame. A computer peripheral device is coupled to an end of the movable arm opposite the end that is coupled to the second frame.