Abstract: Intelligent process management is provided. A start time is determined for an additional process to be run on a worker node within a duration of a sleep state of a task of a process already running on the worker node by adding a first defined buffer time to a determined start time of the sleep state of the task. A backfill time is determined for the additional process by subtracting a second defined buffer time from a determined end time of the sleep state of the task. A scheduling plan is generated for the additional process based on the start time and the backfill time corresponding to the additional process. The scheduling plan is executed to run the additional process on the worker node according to the start time and the backfill time corresponding to the additional process.

Abstract: A liquid cooling device includes a base plate, a cooling body, and a cover plate. The cooling body includes a frame. A cooling layer is provided in the frame and a reflux layer is provided above the cooling layer. The cooling layer is provided with a plurality of cooling channels extending from a center portion of the cooling body to the frame. The reflux layer is provided with a plurality of reflux channels in communication with the plurality of cooling channels. A periphery of the reflux layer is provided with a drainage flow channel in communication with the plurality of the reflux channels. A center portion of the cover plate being provided with a liquid inlet in communication with the plurality of cooling channels, and the cover plate is further provided with a liquid outlet in communication with the drainage flow channel.

Abstract: A method for dynamic random access memory (DRAM) control with adjustable page size, including the following steps. During power-up initialization, a DRAM type is identified and a page mask for the DRAM type is set. Upon receipt of a DRAM access, an adjustable page portion of an internal address for the prior DRAM access and an adjustable page portion of an internal address for a next DRAM access are respectively determined in accordance with the page mask. A first portion of the internal address for the prior DRAM access is compared to a first portion of the internal address for the next DRAM access, and the adjustable page portion of the internal address for the prior DRAM access is compared to the adjustable page portion of the internal address for the next DRAM access, to determine whether the next DRAM access is a page hit or miss.

Abstract: A method and apparatus for refreshing dynamic memory is provided. The apparatus includes an ahead refresh controller having an ahead queue for refreshing dynamic random access memory (DRAM) when the memory request bus is idle. In such a way that no dynamic RAM bandwidth is wasted. The apparatus also comprises a normal refresh controller having a normal queue. Giving the normal refresh request in the normal priority unless the normal queue is full. The present invention allows the refresh cycles to gather on the basis of events to minimize the overheads. In other words, even when the system is running in peak performance, the normal refresh controller can largely compact the refresh cycles by means of the normal queue to decrease occurrence of interruption.