Patents by Inventor Yi-Ming Lee

Yi-Ming Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240174716
    Abstract: The present invention relates to transporter peptides that can bind to a transferrin receptor (TfR). The transporter peptides can be conjugated covalently or noncovalently to an effector agent to form a transporter peptide conjugate, or a nucleic acid encoding the transporter peptides and an effector agent is expressed to form a recombinant transporter peptide conjugate. The transporter peptide conjugate and the recombinant transporter peptide conjugate deliver the effector agent to a target by binding to a TfR. Binding of the transporter peptides to transferrin receptors on cells of a tissue barrier induces transcytosis of the cells, thereby transporting the transporter peptide conjugate across the tissue barrier. The transporter peptides can serve as a drug delivery system and used for treatment of central nervous system (CNS) diseases.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 30, 2024
    Inventors: Jia-Ming CHANG, Yi-RU LEE
  • Publication number: 20240160331
    Abstract: An audio and visual equipment and a method are provided. The audio and visual equipment includes a terminal device including a display. A user interface is displayed by the display. The user interface selectively displays one of a background selection page for selecting a background image, a stack layout selection page for selecting a layout pattern, a presentation selection page for selecting a presentation image, and an object rotation control page for controlling a position of an augmented reality object image. The terminal device provides a control signal according to a selection of the user interface. The terminal device receives a composite image associated with the selection of the user interface. The composite image is displayed by the display. The composite image includes at least one predetermined stacking sequence formed by a person image, the background image, and the at least one of the augmented reality object image and the presentation image.
    Type: Application
    Filed: January 23, 2024
    Publication date: May 16, 2024
    Applicant: Optoma China Co., Ltd
    Inventors: Kai-Ming Guo, Tian-Shen Wang, Zi-Xiang Xiao, Yi-Wei Lee
  • Publication number: 20240162313
    Abstract: A method for forming a high electron mobility transistor is disclosed. A mesa structure having a channel layer and a barrier layer is formed on a substrate. The mesa structure has two first edges extending along a first direction and two second edges extending along a second direction. A passivation layer is formed on the substrate and the mesa structure. A first opening and a plurality of second openings connected to a bottom surface of the first opening are formed and through the passivation layer, the barrier layer and a portion of the channel layer. In a top view, the first opening exposes the two first edges of the mesa structure without exposing the two second edges of the mesa structure. A metal layer is formed in the first opening and the second openings thereby forming a contact structure.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, Chun-Liang Hou, Wen-Jung Liao, Chun-Ming Chang, Yi-Shan Hsu, Ruey-Chyr Lee
  • Patent number: 11984489
    Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiu Liu, Feng-Cheng Yang, Tsung-Lin Lee, Wei-Yang Lee, Yen-Ming Chen, Yen-Ting Chen
  • Publication number: 20240154015
    Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.
    Type: Application
    Filed: March 22, 2023
    Publication date: May 9, 2024
    Inventors: Jui-Lin CHEN, Hsin-Wen SU, Chih-Ching WANG, Chen-Ming LEE, Chung-I YANG, Yi-Feng TING, Jon-Hsu HO, Lien-Jung HUNG, Ping-Wei WANG
  • Publication number: 20240133949
    Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 25, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Lin Yang, Chin-Wei Lin, Po-Chao Tsao, Tung-Hsing Lee, Chia-Jung Ni, Chi-Ming Lee, Yi-Ju Ting
  • Patent number: 11955397
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 9, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
  • Patent number: 11950491
    Abstract: A semiconductor mixed material comprises an electron donor, a first electron acceptor and a second electron acceptor. The first electron donor is a conjugated polymer. The energy gap of the first electron acceptor is less than 1.4 eV. At least one of the molecular stackability, ?-?*stackability, and crystallinity of the second electron acceptor is smaller than the first electron acceptor. The electron donor system is configured to be a matrix to blend the first electron acceptor and the second electron acceptor. The present invention also provides an organic electronic device including the semiconductor mixed material.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: April 2, 2024
    Assignee: RAYNERGY TEK INCORPORATION
    Inventors: Yi-Ming Chang, Chuang-Yi Liao, Wei-Long Li, Yu-Tang Hsiao, Chun-Chieh Lee, Chia-Hua Li, Huei-Shuan Tan
  • Publication number: 20240105454
    Abstract: A method for manufacturing a semiconductor device is described. The method includes the following steps. A low-dimensional material (LDM) layer is formed on a semiconductor substrate, wherein the LDM layer includes sublayers stacked upon one another. A plasma treatment is performed to the LDM layer to transform at least one sublayer into an oxide layer, wherein the plasma treatment is performed under a temperature equivalent to or lower than about 80 degrees Celsius. At least one electrode is disposed over the oxide layer.
    Type: Application
    Filed: March 2, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Wei-Sheng Yun, Yi-Tse HUNG, Shao-Ming YU, Meng-Zhan Li
  • Patent number: 11921971
    Abstract: A live broadcasting recording equipment, a live broadcasting recording system and a live broadcasting recording method are provided. The live broadcasting recording equipment includes a camera, a processing device, and a terminal device. The camera captures images to provide photographic data. The processing device executes background removal processing on the photographic data to generate a person image. The terminal device communicates with the processing device and has a display. The processing device executes multi-layer processing to fuse the person image, a three-dimensional virtual reality background image, an augmented reality object image, and a presentation image, and generate a composite image. After an application gateway of the processing device recognizes a login operation of the terminal device, the processing device outputs the composite image to the terminal device, so that the display of the terminal device displays the composite image.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 5, 2024
    Assignee: Optoma China Co., Ltd
    Inventors: Kai-Ming Guo, Tian-Shen Wang, Zi-Xiang Xiao, Yi-Wei Lee
  • Patent number: 11921930
    Abstract: An input device for an information handling system ay detect an adjustment to a position of a damping medium of a linear magnetic ram of the input device. The input device may generate haptic feedback based on the detected adjustment to the position of the damping medium of the linear magnetic ram of the input device.
    Type: Grant
    Filed: January 4, 2023
    Date of Patent: March 5, 2024
    Assignee: Dell Products L.P.
    Inventors: Yi-Ming Chou, Chiu-Jung Tsen, Hsu-Feng Lee, Gerald Rene Pelissier
  • Patent number: 11917230
    Abstract: A system and method for maximizing bandwidth in an uplink for a 5G communication system is disclosed. Multiple end devices generate image streams. A gateway is coupled to the end devices. The gateway includes a gateway monitor agent collecting utilization rate data of the gateway and an image inspector collecting inspection data from the received image streams. An edge server is coupled to the gateway. The edge server includes an edge server monitor agent collecting utilization rate data of the edge server. An analytics manager is coupled to the gateway and the edge server. The analytics manager is configured to determine an allocation strategy based on the collected utilization rate data from the gateway and the edge server.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: February 27, 2024
    Assignee: Quanta Cloud Technology Inc.
    Inventors: Yi-Neng Zeng, Keng-Cheng Liu, Wei-Ming Huang, Shih-Hsun Lai, Ji-Jeng Lin, Chia-Jui Lee, Liao Jin Xiang
  • Patent number: 11493977
    Abstract: An electronic device includes a processor, a battery, a charging circuit, a controller, and an arithmetic logic unit. The processor is capable of operating at a preset frequency or a low frequency. The charging circuit is electrically connected to an external power supply and a battery and transmits a disconnection signal and to be powered by the battery when the external power supply and the charging circuit are changed from a connected state to a disconnected state. The controller is configured to transmit a first control signal when the external power supply and the charging circuit are changed from the connected state to the disconnected state. The arithmetic logic unit is configured to transmit a frequency reduction signal to the processor according to the disconnection signal and the first control signal, so that the processor reduces the preset frequency to the low frequency and operates at the low frequency.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: November 8, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Chia-Liang Wei, Shiuan-Shuo Shiu, Ssu-Yun Chen, Jei-Hsiang Ma, Yi-Ming Lee, Chih-Wei Chung, Ming-You Jiang, Wei-Hao Lee
  • Publication number: 20220043499
    Abstract: An electronic device includes a processor, a battery, a charging circuit, a controller, and an arithmetic logic unit. The processor is capable of operating at a preset frequency or a low frequency. The charging circuit is electrically connected to an external power supply and a battery and transmits a disconnection signal and to be powered by the battery when the external power supply and the charging circuit are changed from a connected state to a disconnected state. The controller is configured to transmit a first control signal when the external power supply and the charging circuit are changed from the connected state to the disconnected state. The arithmetic logic unit is configured to transmit a frequency reduction signal to the processor according to the disconnection signal and the first control signal, so that the processor reduces the preset frequency to the low frequency and operates at the low frequency.
    Type: Application
    Filed: March 11, 2021
    Publication date: February 10, 2022
    Inventors: Chia-Liang Wei, Shiuan-Shuo Shiu, Ssu-Yun Chen, Jei-Hsiang Ma, Yi-Ming Lee, Chih-Wei Chung, Ming-You Jiang, Wei-Hao Lee
  • Patent number: 9525236
    Abstract: The present invention is to provide a waterproof connector with a gluing plane coated by waterproof glue, which includes an isolation base having a gluing plane formed at a rear end thereof, a plurality of first and second connection terminals each having a rear end exposed out of the gluing plane and an isolation sheet positioned between the first and second connection terminals; a metal casing for allowing the gluing plane to be positioned therein near a back opening thereof while the isolation base is inserted into the metal casing via the back opening; and a waterproof glue layer formed by coating a waterproof glue along where the gluing plane and an inner surface of the metal casing are abutted with each other. Thus, when the waterproof glue is hardened to form the waterproof glue layer, cracks between the metal casing and the isolation base are fully and watertightly filled.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: December 20, 2016
    Assignee: SIMULA TECHNOLOGY INC.
    Inventor: Yi-Ming Lee
  • Patent number: 9437957
    Abstract: The present invention is to provide a waterproof connector having internally concealed grounding pin, which includes an outer housing having an isolation layer covered on a metal frame thereof by injection molding to form at least one grounding part exposed to a first accommodating space therein and at least one outer grounding pin exposed out of the isolation layer; an inner casing made of metal material and having at least one inner grounding pin abutted against the grounding part when the inner casing is mounted inside the outer housing; a terminal block formed by plastic integrally, having a plurality of connection terminals passing therethrough, and mounted inside the inner casing; and a waterproof glue layer watertightly filled in the rear ends of the outer housing and inner casing. Since the inner grounding pin is fully concealed inside the outer housing, the moisture can no more pass through the connector accordingly.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: September 6, 2016
    Assignee: SIMULA TECHNOLOGY INC.
    Inventor: Yi-Ming Lee
  • Publication number: 20160164218
    Abstract: The present invention is to provide a waterproof connector having internally concealed grounding pin, which includes an outer housing having an isolation layer covered on a metal frame thereof by injection molding to form at least one grounding part exposed to a first accommodating space therein and at least one outer grounding pin exposed out of the isolation layer; an inner casing made of metal material and having at least one inner grounding pin abutted against the grounding part when the inner casing is mounted inside the outer housing; a terminal block formed by plastic integrally, having a plurality of connection terminals passing therethrough, and mounted inside the inner casing; and a waterproof glue layer watertightly filled in the rear ends of the outer housing and inner casing. Since the inner grounding pin is fully concealed inside the outer housing, the moisture can no more pass through the connector accordingly.
    Type: Application
    Filed: February 19, 2015
    Publication date: June 9, 2016
    Applicant: SIMULA TECHNOLOGY INC.
    Inventor: Yi-Ming LEE
  • Publication number: 20160164217
    Abstract: The present invention is to provide a waterproof connector with a gluing plane coated by waterproof glue, which includes an isolation base having a gluing plane formed at a rear end thereof, a plurality of first and second connection terminals each having a rear end exposed out of the gluing plane and an isolation sheet positioned between the first and second connection terminals; a metal casing for allowing the gluing plane to be positioned therein near a back opening thereof while the isolation base is inserted into the metal casing via the back opening; and a waterproof glue layer formed by coating a waterproof glue along where the gluing plane and an inner surface of the metal casing are abutted with each other. Thus, when the waterproof glue is hardened to form the waterproof glue layer, cracks between the metal casing and the isolation base are fully and watertightly filled.
    Type: Application
    Filed: February 19, 2015
    Publication date: June 9, 2016
    Applicant: SIMULA TECHNOLOGY INC.
    Inventor: Yi-Ming LEE
  • Patent number: 8460021
    Abstract: The present invention is to provide a card insert/eject mechanism, which includes an insulating seat formed with a receiving space and a track groove; a metal housing covering the receiving space and track groove and having a position-limiting resilient plate at a bottom surface thereof; a sliding block slidable along the track groove and laterally provided with a pushing portion that extends into the receiving space thereby, when an electronic card pushes the pushing portion, the sliding block is moved against rear end of the insulating seat; a resilient element provided in the track groove for applying a force to rear end of the sliding block; and a release bar disposed in the track groove for releasing the position-limiting resilient plate and enabling the sliding block to push the electronic card out of the receiving space, so as to effectively solve the insecure card engagement problem in conventional push-push connectors.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: June 11, 2013
    Assignee: Simula Technology Inc.
    Inventors: Yi-Ming Lee, Chien-Yeh Lee
  • Publication number: 20130130527
    Abstract: The present invention is to provide a card insert/eject mechanism, which includes an insulating seat formed with a receiving space and a track groove; a metal housing covering the receiving space and track groove and having a position-limiting resilient plate at a bottom surface thereof; a sliding block slidable along the track groove and laterally provided with a pushing portion that extends into the receiving space thereby, when an electronic card pushes the pushing portion, the sliding block is moved against rear end of the insulating seat; a resilient element provided in the track groove for applying a force to rear end of the sliding block; and a release bar disposed in the track groove for releasing the position-limiting resilient plate and enabling the sliding block to push the electronic card out of the receiving space, so as to effectively solve the insecure card engagement problem in conventional push-push connectors.
    Type: Application
    Filed: November 23, 2011
    Publication date: May 23, 2013
    Applicant: SIMULA TECHNOLOGY INC.
    Inventors: Yi-Ming LEE, Chien-Yeh LEE