Patents by Inventor Yi-Nan Chen
Yi-Nan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8692245Abstract: The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.Type: GrantFiled: August 21, 2011Date of Patent: April 8, 2014Assignee: Nanya Technology Corp.Inventors: Tse-Yao Huang, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8692318Abstract: A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.Type: GrantFiled: May 10, 2011Date of Patent: April 8, 2014Assignee: Nanya Technology Corp.Inventors: Chin-Te Kuo, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8662963Abstract: A chemical mechanical polishing (CMP) system includes a wafer polishing unit producing a used slurry; a slurry treatment system for receiving and treating the used slurry to thereby produce an extracted basic solution; and a post-CMP cleaning unit utilizing the extracted basic solution to wash a polished wafer surface. The post-CMP cleaning unit includes a plurality of rollers for supporting and rotating a wafer, a brush for scrubbing the wafer, and a spray bar disposed in proximity to the brush for spraying the extracted basic solution onto the polished wafer surface.Type: GrantFiled: May 12, 2011Date of Patent: March 4, 2014Assignee: Nanya Technology Corp.Inventors: Li-Chung Liu, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8642479Abstract: A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.Type: GrantFiled: July 14, 2011Date of Patent: February 4, 2014Assignee: Nanya Technology CorporationInventors: Chih-Ching Lin, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8614467Abstract: A method of gate work function adjustment includes the steps as follow. First, a substrate is provided, wherein a metal gate is disposed on the substrate, a source doping region and a drain doping region are disposed in the substrate at opposite sites of the metal gate, wherein the metal gate is divided into a source side adjacent to the source doping region, and a drain side adjacent to the drain doping region. Later, a mask layer is formed to cover the source doping region and the drain doping region. After that, an implantation process is performed to implant nitrogen into the metal gate so as to make a first nitrogen concentration of the source side higher than a second nitrogen concentration of the drain side. Finally, the mask layer is removed.Type: GrantFiled: April 7, 2011Date of Patent: December 24, 2013Assignee: Nanya Technology Corp.Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8604542Abstract: A circuit structure with a capacitor or a resistor includes a semiconductor substrate, a first conductive region positioned in the semiconductor substrate, a plurality of second conductive regions and third conductive regions positioned in the first conductive region, a first depletion region positioned between the first conductive region and the third conductive region, a second depletion region positioned between the second conductive region and the third conductive region, and a plurality of separating regions positioned in the first conductive region, configured to separate the second and the third conductive regions. In operation, a first voltage is applied to the separating region to control the capacitance or the resistance of the circuit structure. A second voltage is applied to the first conductive region and a third voltage is applied to the second conductive region to measure the capacitance and the resistance of the circuit structure.Type: GrantFiled: August 23, 2011Date of Patent: December 10, 2013Assignee: Nan Ya Technology CorporationInventors: Jeng Hsing Jang, Yi Nan Chen, Hsien Wen Liu
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Patent number: 8592320Abstract: A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate.Type: GrantFiled: August 15, 2011Date of Patent: November 26, 2013Assignee: Nanya Technology CorporationInventors: Chih-Ching Lin, Yi-Nan Chen, Hsien-Wen Liu
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Publication number: 20130307067Abstract: A slit recess channel gate is provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer.Type: ApplicationFiled: August 5, 2013Publication date: November 21, 2013Applicant: NANYA TECHNOLOGY CORP.Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8551881Abstract: A method of bevel trimming a three dimensional (3D) semiconductor device is disclosed, comprising providing a substrate with stack layers thereon and through substrate vias (TSV) therein, wherein an edge of the substrate is curved, performing a bevel trimming step to the curved edge of the substrate for obtaining a planar edge, and thinning the substrate to expose the through substrate vias.Type: GrantFiled: April 25, 2011Date of Patent: October 8, 2013Assignee: Nanya Technology CorporationInventors: Shing-Yih Shih, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8546234Abstract: A semiconductor process is provided. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. Using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening and the side wall is covered by the mask layer. Using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion. A conversion process is performed, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion.Type: GrantFiled: June 6, 2011Date of Patent: October 1, 2013Assignee: Nanya Technology CorporationInventors: Wen-Chieh Wang, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8545289Abstract: A distance monitoring device is provided. The device is suitable for a chemical mechanical polishing (CMP) apparatus. A polishing head of the CMP apparatus includes a frame and a membrane. The membrane is mounted on the frame, and a plurality of air bags is formed by the membrane and the frame in the polishing head. The distance monitoring device includes a plurality of distance detectors disposed on the frame corresponding to the air bags respectively to set a location of each of the distance detectors on the frame as a reference point, wherein each of the distance detectors is configured to measure a distance between each of the reference points and the membrane.Type: GrantFiled: April 13, 2011Date of Patent: October 1, 2013Assignee: Nanya Technology CorporationInventors: Chien-Mao Liao, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8536056Abstract: A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other.Type: GrantFiled: August 22, 2011Date of Patent: September 17, 2013Assignee: Nanya Technology CorporationInventors: Kuo-Hui Su, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8533638Abstract: A model of defining a photoresist pattern collapse rule is provided. A portion of the photoresist pattern which corresponds to a second line pattern of a photomask layout is defined as non-collapse patterns if d?5a and c?1.5b or if 5a>d?3a and c?1.2b, wherein b is the widths of two first line patterns, c is the width of a second line pattern of the photomask layout, and a and d are distances between the second line pattern and the two first line patterns. Accordingly, a photomask layout, a semiconductor substrate and a method for improving photoresist pattern collapse for post-optical proximity correction are also provided.Type: GrantFiled: April 5, 2011Date of Patent: September 10, 2013Assignee: Nanya Technology CorporationInventors: Kuo Kuei Fu, Yi Nan Chen, Hsien Wen Liu
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Patent number: 8530306Abstract: A slit recess channel gate is further provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. The present invention also provides a method of forming the slit recess channel gate.Type: GrantFiled: May 27, 2011Date of Patent: September 10, 2013Assignee: Nanya Technology Corp.Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8525262Abstract: The present invention disclosed a recessed gate transistor with buried fins. The recessed gate transistor with buried fins is disposed in an active region on a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate, and sandwich the active region. A gate structure is disposed in the semiconductor substrate, wherein the gate structure includes: an upper part and a lower part. The upper part is disposed in the active region and a lower part having a front fin disposed in one of the two isolation regions, at least one middle fin disposed in the active region, and a last fin disposed in the other one of the two isolation regions, wherein the front fin are both elliptic cylindrical.Type: GrantFiled: April 7, 2011Date of Patent: September 3, 2013Assignee: Nanya Technology Corp.Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8497568Abstract: A monitoring pattern for pattern stitch in double patterning is provided with a plurality of pattern cuts that include at least one line-ended cut and at least one non-line-ended cut, wherein every pattern cut has a stitching critical dimension (CD). A semiconductor wafer having at least one target pattern corresponding to the monitoring pattern is also provided. A method for monitoring pattern stitch can be preformed to check for pattern cut displacement in stitching areas and to increase reliability and printability of layouts, by comparing corresponding stitching critical dimensions of the target pattern and the monitoring pattern.Type: GrantFiled: April 5, 2011Date of Patent: July 30, 2013Assignee: Nanya Technology CorporationInventors: Kuo Kuei Fu, Yi Nan Chen, Hsien Wen Liu
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Patent number: 8487397Abstract: An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.Type: GrantFiled: April 25, 2011Date of Patent: July 16, 2013Assignee: Nanya Technology CorporationInventors: Jar-Ming Ho, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8486834Abstract: The disclosure provides a method for manufacturing a memory device, including: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; and performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide.Type: GrantFiled: May 24, 2011Date of Patent: July 16, 2013Assignee: Nanya Technology CorporationInventors: Ping Hsu, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8476764Abstract: A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; and a plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region.Type: GrantFiled: September 18, 2011Date of Patent: July 2, 2013Assignee: Nanya Technology Corp.Inventors: Tse-Yao Huang, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8476704Abstract: A circuit structure including a semiconductor substrate having a depression; a first insulating layer positioned on the surface of the depression; a bottom conductor positioned in a bottom portion of the depression, wherein the bottom conductor is connected to an external bias through a plurality of longer vertical contact plugs; an upper conductor positioned in an upper portion of the depression, wherein the upper conductor is connected to a plurality of shorter vertical contact plugs, and a top surface of the upper conductor is higher than a depression-bearing surface of the semiconductor substrate; and a second insulating layer positioned between the bottom conductor and the upper conductor.Type: GrantFiled: August 19, 2011Date of Patent: July 2, 2013Assignee: Nan Ya Technology CorporationInventors: Jeng Hsing Jang, Yi Nan Chen, Hsien Wen Liu