Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor comprises a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further comprises shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further comprises a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.

Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes the conductive liner contacting the portion of the surface of the first conductive layer. A trench structure is formed on the via structure in the dielectric without the conductive liner layer in the trench.

Abstract: A method and system for determining the dielectric constant of a low-k dielectric film on a production substrate include measuring the electronic component of the dielectric constant using an ellipsometer, measuring the ionic component of the dielectric constant using an IR spectrometer, measuring the overall dielectric constant using a microwave spectrometer and deriving the dipolar component of the dielectric constant. The measurements and determination are non-contact and may be carried out on a production device that is further processed following the measurements.

Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes the conductive liner contacting the portion of the surface of the first conductive layer. A trench structure is formed on the via structure in the dielectric without the conductive liner layer in the trench.

Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure comprises a conductive layer in a dielectric layer, and a via hole in the dielectric layer for exposing a portion of a surface of the conductive layer. A conductive liner covers the exposed surface of the first conductive layer. A trench is formed on the via hole in the dielectric without the conductive liner layer in the trench. Dual damascene structures and fabrications methods are also disclosed. Following the fabrication methods of the via hole and trench structures, a conductive layer is further formed in the via hole and trench structures.

Abstract: A method for fabricating dual damascene structures having improved IC performance and reduced RC delay characteristics is provided. In one embodiment, a substrate with an etch stop layer formed thereon is provided. A dielectric layer is formed on the etch stop layer and an anti-reflective coating layer is formed on the dielectric layer. A first patterned photoresist layer having a via hole pattern is formed on the anti-reflective coating layer. The via hole pattern is thereafter etched through the anti-reflective coating layer, the dielectric layer, and the etch stop layer to form a via hole. A sacrificial via fill layer is filled in the via hole. A second patterned photoresist layer having a trench pattern is formed above the sacrificial via fill layer. The trench pattern is etched into the sacrificial via fill layer, the anti-reflective coating layer, and the dielectric layer to form a trench. The sacrificial via fill layer is removed in the via hole.

Abstract: An opening in a semiconductor device with improved step coverage. The opening comprises a dielectric layer overlying a substrate, having at least one via opening to expose the substrate. The via opening comprises a step region in the upper portion of the via opening and a concave profile region with respect to the dielectric layer in the lower portion of the via opening. A semiconductor device with the opening is also disclosed.

Abstract: A semiconductor device. A diffusion barrier layer overlies a substrate. An adhesion promoting layer overlies the diffusion barrier layer. A first dielectric layer between the diffusion barrier layer and the adhesion promoting layer comprises at least one via opening through the diffusion barrier layer and the adhesion promoting layer. A second dielectric layer overlies the adhesion promoting layer, comprising a trench opening above the via opening. A metal interconnect fills the via and trench openings.

Abstract: Methods for fabricating interconnect structures implementing air gaps therein is provided. In one embodiment, a semiconductor substrate with a first barrier layer formed thereon is provided. A first dielectric layer is formed above the barrier layer. The first dielectric layer is thereafter patterned and etched to form a plurality of stakes having first openings therebetween, the plurality of stakes for providing mechanical supporting strength for the interconnect structure. A sacrificial layer is formed in the first openings and above the plurality of stakes. A hard mask layer is formed above the sacrificial layer. A light sensitive layer is formed over the hard mask layer and is thereafter patterned to define a pattern therein. The hard mask layer, the sacrificial layer, and the first barrier layer are etched according to the pattern in the light sensitive layer to form second openings. The second openings are filled with a conductive material to form metal lines.

Abstract: A method and system for determining the dielectric constant of a low-k dielectric film on a production substrate include measuring the electronic component of the dielectric constant using an ellipsometer, measuring the ionic component of the dielectric constant using an IR spectrometer, measuring the overall dielectric constant using a microwave spectrometer and deriving the dipolar component of the dielectric constant. The measurements and determination are non-contact and may be carried out on a production device that is further processed following the measurements.

Abstract: Methods for fabricating interconnect structures implementing air gaps therein is provided. In one embodiment, a semiconductor substrate with a first barrier layer formed thereon is provided. A first dielectric layer is formed above the barrier layer. The first dielectric layer is thereafter patterned and etched to form a plurality of stakes having first openings therebetween, the plurality of stakes for providing mechanical supporting strength for the interconnect structure. A sacrificial layer is formed in the first openings and above the plurality of stakes. A hard mask layer is formed above the sacrificial layer. A light sensitive layer is formed over the hard mask layer and is thereafter patterned to define a pattern therein. The hard mask layer, the sacrificial layer, and the first barrier layer are etched according to the pattern in the light sensitive layer to form second openings. The second openings are filled with a conductive material to form metal lines.

Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure comprises a conductive layer in a dielectric layer, and a via hole in the dielectric layer for exposing a portion of a surface of the conductive layer. A conductive liner covers the exposed surface of the first conductive layer. A trench is formed on the via hole in the dielectric without the conductive liner layer in the trench. Dual damascene structures and fabrications methods are also disclosed. Following the fabrication methods of the via hole and trench structures, a conductive layer is further formed in the via hole and trench structures.

Abstract: Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.

Abstract: A new method for forming a single or a double damascene interconnect structure is provided in which after the damascene interconnect structure is formed, in which a plasma ashing process is used to remove the photoresist mask used during the photolithography process, the trench-level intermetal dielectric layer is removed leaving gaps between the trench-level interconnect structure. The gaps are then filled with a new layer of ultra-low-k dielectric material providing an ultra-low-k intermetal dielectric layer that has not been damaged by the plasma ashing process.

Abstract: A plasma containing 5–10% oxygen and 90–95% of an inert gas strips photoresist from over a low-k dielectric material formed on or in a semiconductor device. The inert gas may be nitrogen, hydrogen, or a combination thereof, or it may include at least one of nitrogen, hydrogen, NH3, Ar, He, and CF4. The operating pressure of the plasma may range from 1 millitorr to 150 millitor. The plasma removes photoresist, the hard skin formed on photoresist during aggressive etch processes, and polymeric depositions formed during etch processes. The plasma strips photoresist at a rate sufficiently high for production use and does not appreciably attack carbon-containing low-k dielectric materials. An apparatus including a plasma tool containing a semiconductor substrate and the low oxygen-content plasma, is also provided.

Abstract: A plasma processing operation uses a gas mixture of N2 and H2 to both remove a photoresist film and treat a low-k dielectric material. The plasma processing operation prevents degradation of the low-k material by forming a protective layer on the low-k dielectric material. Carbon from the photoresist layer is activated and caused to complex with the low-k dielectric, maintaining a suitably high carbon content and a suitably low dielectric constant. The plasma processing operation uses a gas mixture with H2 constituting at least 10%, by volume, of the gas mixture.

Abstract: A method for forming a dual damascene interconnect structure provides an intermetal dielectric that includes a spin-on low-k dielectric material formed over a CVD low-k dielectric material. A via opening is formed by etching through the spin-on low-k dielectric material and the CVD low-k dielectric material and a plug material is introduced to fill the via opening. A highly selective trench etching operation etches a trench in the upper, spin-on low-k dielectric material and removes the plug material from the via without attacking the lower CVD low-k dielectric material to form the dual damascene opening which is then filled with a conductive interconnect material. The intermetal dielectric formed of multiple low-k dielectric layers provides advantageous electrical and mechanical properties.

Abstract: A plasma containing 5-10% oxygen and 90-95% of an inert gas strips photoresist from over a low-k dielectric material formed on or in a semiconductor device. The inert gas may be nitrogen, hydrogen, or a combination thereof, or it may include at least one of nitrogen, hydrogen, NH3, Ar, He, and CF4. The operating pressure of the plasma may range from 1 millitorr to 150 millitor. The plasma removes photoresist, the hard skin formed on photoresist during aggressive etch processes, and polymeric depositions formed during etch processes. The plasma strips photoresist at a rate sufficiently high for production use and does not appreciably attack carbon-containing low-k dielectric materials. An apparatus including a plasma tool containing a semiconductor substrate and the low oxygen-content plasma, is also provided.

Abstract: A method for fabricating dual damascene structures having improved IC performance and reduced RC delay characteristics is provided. In one embodiment, a substrate with an etch stop layer formed thereon is provided. A dielectric layer is formed on the etch stop layer and an anti-reflective coating layer is formed on the dielectric layer. A first patterned photoresist layer having a via hole pattern is formed on the anti-reflective coating layer. The via hole pattern is thereafter etched through the anti-reflective coating layer, the dielectric layer, and the etch stop layer to form a via hole. A sacrificial via fill layer is filled in the via hole. A second patterned photoresist layer having a trench pattern is formed above the sacrificial via fill layer. The trench pattern is etched into the sacrificial via fill layer, the anti-reflective coating layer, and the dielectric layer to form a trench. The sacrificial via fill layer is removed in the via hole.

Abstract: Methods for fabricating interconnect structures implementing air gaps therein is provided. In one embodiment, a semiconductor substrate with a first barrier layer formed thereon is provided. A first dielectric layer is formed above the barrier layer. The first dielectric layer is thereafter patterned and etched to form a plurality of stakes having first openings therebetween, the plurality of stakes for providing mechanical supporting strength for the interconnect structure. A sacrificial layer is formed in the first openings and above the plurality of stakes. A hard mask layer is formed above the sacrificial layer. A light sensitive layer is formed over the hard mask layer and is thereafter patterned to define a pattern therein. The hard mask layer, the sacrificial layer, and the first barrier layer are etched according to the pattern in the light sensitive layer to form second openings. The second openings are filled with a conductive material to form metal lines.