Patents by Inventor Yi Shan

Yi Shan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11997066
    Abstract: A data transmission system and method thereof for edge computing are provided. A terminal mobile station international subscriber directory number (MSISDN) and a terminal IP of a target terminal are obtained with a domain name system (DNS) by a device providing communication services from the data transmission system. After data packets are sent to the data transmission system, if the target terminal is in an idle mode, a paging message is sent by a terminal wake-up module to enable the target terminal to return to a connected mode for communication. Before a connection is established between the data transmission system and the target terminal, downlink data packets can be temporarily stored, and the packets can be sent after the target terminal is in the connected mode. A computer readable medium for executing the data transmission method is also provided.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: May 28, 2024
    Assignee: CHUNGHWA TELECOM CO., LTD.
    Inventors: Yi-Hua Wu, Wei-Shan Lu, Kang-Hao Lo, Cheng-Yi Chien, Yueh-Feng Li, Ling-Chih Kao
  • Publication number: 20240162313
    Abstract: A method for forming a high electron mobility transistor is disclosed. A mesa structure having a channel layer and a barrier layer is formed on a substrate. The mesa structure has two first edges extending along a first direction and two second edges extending along a second direction. A passivation layer is formed on the substrate and the mesa structure. A first opening and a plurality of second openings connected to a bottom surface of the first opening are formed and through the passivation layer, the barrier layer and a portion of the channel layer. In a top view, the first opening exposes the two first edges of the mesa structure without exposing the two second edges of the mesa structure. A metal layer is formed in the first opening and the second openings thereby forming a contact structure.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, Chun-Liang Hou, Wen-Jung Liao, Chun-Ming Chang, Yi-Shan Hsu, Ruey-Chyr Lee
  • Patent number: 11978640
    Abstract: In a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. A location of the shifted opening is laterally shifted from an original location of the opening.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: May 7, 2024
    Inventors: Yi-Chen Lo, Yi-Shan Chen, Chih-Kai Yang, Pinyen Lin
  • Publication number: 20240133918
    Abstract: In a method for obtaining the equivalent oxide thickness of a dielectric layer, a first semiconductor capacitor including a first silicon dioxide layer and a second semiconductor capacitor including a second silicon dioxide layer are provided and a modulation voltage is applied to the semiconductor capacitors to measure a first scanning capacitance microscopic signal and a second scanning capacitance microscopic signal. According to the equivalent oxide thicknesses of the silicon dioxide layers and the scanning capacitance microscopic signals, an impedance ratio is calculated. The modulation voltage is applied to a third semiconductor capacitor including a dielectric layer to measure a third scanning capacitance microscopic signal. Finally, the equivalent oxide thickness of the dielectric layer is obtained according to the equivalent oxide thickness of the first silicon dioxide layer, the first scanning capacitance microscopic signal, third scanning capacitance microscopic signal, and the impedance ratio.
    Type: Application
    Filed: April 12, 2023
    Publication date: April 25, 2024
    Inventors: MAO-NAN CHANG, CHI-LUN LIU, HSUEH-LIANG CHOU, YI-SHAN WU, CHIAO-JUNG LIN, YU-HSUN HSUEH
  • Patent number: 11931187
    Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 19, 2024
    Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung University
    Inventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
  • Patent number: 11901176
    Abstract: A method for fabricating a semiconductor arrangement is provided. The method includes forming a first dielectric layer and forming a first semiconductive layer over the first dielectric layer. The first semiconductive layer is patterned to form a patterned first semiconductive layer. The first dielectric layer is patterned using the patterned first semiconductive layer to form a patterned first dielectric layer. A second semiconductive layer is formed over the patterned first dielectric layer and the patterned first semiconductive layer.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yi-Shan Chen, Hao-Heng Liu
  • Patent number: 11872471
    Abstract: A braking mechanism of a wheeled device is provided, including: a main body, configured to be connected to the wheeled device including at least one wheel; an adjusting member, disposed on the main body and including a rod and a first abutting member adjustably positioned on the rod; a braking member, movably disposed on the main body; and an elastic member, abutted between the first abutting member and the braking member so that the braking member is biased by the force of the elastic member toward the at least one wheel to frictionally contact the at least one wheel.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: January 16, 2024
    Inventors: Wen-Kuei Liu, Hsiu-Feng Chen, Chao-Hsuan Liu, Yu-Chun Liu, Yi-Shan Liu, Yu-Cheng Liu, Yan-Rui Liu
  • Publication number: 20230378314
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 23, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Bo-Rong Chen, Che-Hung Huang, Chun-Ming Chang, Yi-Shan Hsu, Chih-Tung Yeh, Shin-Chuan Huang, Wen-Jung Liao, Chun-Liang Hou
  • Publication number: 20230369448
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 16, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Bo-Rong Chen, Che-Hung Huang, Chun-Ming Chang, Yi-Shan Hsu, Chih-Tung Yeh, Shin-Chuan Huang, Wen-Jung Liao, Chun-Liang Hou
  • Publication number: 20230356061
    Abstract: A braking mechanism of a wheeled device is provided, including: a main body, configured to be connected to the wheeled device including at least one wheel; an adjusting member, disposed on the main body and including a rod and a first abutting member adjustably positioned on the rod; a braking member, movably disposed on the main body; and an elastic member, abutted between the first abutting member and the braking member so that the braking member is biased by the force of the elastic member toward the at least one wheel to frictionally contact the at least one wheel.
    Type: Application
    Filed: May 3, 2022
    Publication date: November 9, 2023
    Inventors: Wen-Kuei LIU, Hsiu-Feng CHEN, Chao-Hsuan LIU, Yu-Chun LIU, Yi-Shan LIU, Yu-Cheng LIU, Yan-Rui LIU
  • Patent number: 11810856
    Abstract: A power mesh structure for an integrated circuit is provided. A power switch cell is installed on the chip of the integrated circuit to control the switching operations of the power domain. The power meshes of the power mesh structure is specially designed. The power wires with different electrical properties are arranged in the same column or the same row to reduce the layout area of the power mesh on the material layer.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: November 7, 2023
    Assignee: FARADAY TECHNOLOGY CORPORATION
    Inventors: Yi-Shan Li, Chi-Mao Chen, Duc Anh Nguyen, Po-Chen Lo, Shung-Ru Lin
  • Publication number: 20230337998
    Abstract: The present invention relates to a method for measuring muscle mass, including: a first selection step, wherein a frame selection information is obtained by using a frame to select a fascia region from a provided computed tomography image under the condition that the window width ranges from 300 HU to 500 HU and the window level ranges from 40 HU to 50 HU, wherein the selected range of the fascia region includes a muscle; and a second selection step, wherein a muscle information of the muscle is obtained by calculating a pixel value in the frame-selected fascia region under the condition that the HU value of the CT image ranges from -29 HU to 150 HU.
    Type: Application
    Filed: April 20, 2022
    Publication date: October 26, 2023
    Inventors: Yi-Shan TSAI, Yu-Husan Lai, Bow Wang, Cheng-Shih Lai, Chao-Yun Chen, Meng-Jhen Wu, Po-Tsun Kuo, Tsung-Han Lee
  • Publication number: 20230307094
    Abstract: A method for predicting cancer prognosis is disclosed, and the method comprises capturing a reference radiomics and obtaining reference pathological eigenvalues, wherein the reference pathological eigenvalues are based on pathological features of a reference patients, and the pathological features comprise genomic features, gene expression, test values or a combination of two or more thereof. Then, capturing a test radiomics and obtaining test pathological eigenvalues are performed, wherein the test pathological eigenvalues are based on pathological features of a test patients, and the pathological features comprise genomic features, gene expression, test values or a combination of two or more thereof. A mathematical formula is used to calculate a prognostic index based on the aforementioned reference radiomics, reference pathological eigenvalues, test radiomics and test pathological eigenvalues, and the prognostic change risk of the test patient is evaluated according to the prognostic index.
    Type: Application
    Filed: May 4, 2022
    Publication date: September 28, 2023
    Inventors: Chung-I LI, Meng-Ru SHEN, Yi-Shan TSAI, Peng-Chan LIN, Pei-Fang SU, Yi-Huan LIAO, Yu-Husan LAI
  • Publication number: 20230297343
    Abstract: The present disclosure describes programming marking methods. Various examples include: displaying device controls for at least two operating devices associated with a target task to be executed, where the display configures programming logic of the device controls for the operating devices; determining a respective device group to which each of the operating devices belongs; configuring a group tag for the operating device used for marking the device group; and displaying on a second interface a programming flowchart used when the operating devices execute the target task. The programming flowchart includes at least two function blocks. Each of the function blocks is controlled by one operating device to perform one processing action. Each of the function blocks is marked with a group tag matching the operating device. The second interface configures the function blocks and the execution logic between the function blocks.
    Type: Application
    Filed: July 14, 2020
    Publication date: September 21, 2023
    Applicant: Siemens Ltd., China
    Inventors: Xin Jin, Liang Liao, Jun Yi Shan
  • Patent number: D1004056
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: November 7, 2023
    Assignee: GLOBE UNION INDUSTRIAL CORP.
    Inventor: Yi-Shan Chiang
  • Patent number: D1027125
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: May 14, 2024
    Assignee: GLOBE UNION INDUSTRIAL CORP.
    Inventors: Yi-Shan Chiang, Ya-Chieh Lai, Chun-Yi Tu, Wei-Jen Chen, Tun-Yao Tsai
  • Patent number: D1027131
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: May 14, 2024
    Assignee: GLOBE UNION INDUSTRIAL CORP.
    Inventors: Yu-Chien Yang, Yi-Shan Chiang, Ya-Chieh Lai, Chun-Yi Tu, Wei-Jen Chen, Tun-Yao Tsai
  • Patent number: D1029196
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: May 28, 2024
    Assignee: Globe Union Industrial Corp.
    Inventors: Yu-Chien Yang, Yi-Shan Chiang, Ya-Chieh Lai, Chun-Yi Tu, Wei-Jen Chen, Tun-Yao Tsai
  • Patent number: D1029202
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: May 28, 2024
    Assignee: Globe Union Industrial Corp.
    Inventors: Yu-Chien Yang, Yi-Shan Chiang, Ya-Chieh Lai, Chun-Yi Tu, Wei-Jen Chen, Tun-Yao Tsai
  • Patent number: D1029204
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: May 28, 2024
    Assignee: Globe Union Industrial Corp.
    Inventors: Yu-Chien Yang, Yi-Shan Chiang, Ya-Chieh Lai, Chun-Yi Tu, Wei-Jen Chen, Tun-Yao Tsai