Abstract: A drug delivery device including a main housing and a drug delivery module is provided. The main housing has an internal space. The drug delivery module is disposed in the internal space so as to be isolated from an external environment. The drug delivery module includes a drug bottle that contains a liquid drug and a driver that is connected to the drug bottle. The driver is configured to push the liquid drug to pass through a drug nebulization structure of the drug bottle such that the liquid drug is nebulized into a nebulized drug.

Abstract: A semiconductor device includes a gate layer, a channel material layer, a first dielectric layer and source/drain terminals. The gate layer is disposed over a substrate. The channel material layer is disposed over the gate layer, where a material of the channel material layer includes a first low dimensional material. The first dielectric layer is between the gate layer and the channel material layer. The source/drain terminals are in contact with the channel material layer, where the channel material layer is at least partially disposed between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals.

Abstract: A method of manufacturing a dynamic random access memory is provided and includes: forming a hard mask layer on a substrate; forming an opening in the hard mask layer and the substrate; forming a dielectric layer on a sidewall of the opening; forming a first part of a buried word line in a lower part of the opening; forming a hard mask layer on a top surface of the hindering layer, where the hindering layer has overhangs covering top corners of the hard mask layer; depositing a first barrier layer on the substrate through hindrance of the overhangs, where the first barrier layer covers the hindering layer and a top surface of the first part and exposes the dielectric layer on the sidewall of the opening; and forming a first conductive layer in the opening, where a sidewall of the first conductive layer contacts the dielectric layer.

Abstract: A method of manufacturing a dynamic random access memory is provided and includes: forming a hard mask layer on a substrate; forming an opening in the hard mask layer and the substrate; forming a dielectric layer on a sidewall of the opening; forming a first part of a buried word line in a lower part of the opening; forming a hard mask layer on a top surface of the hindering layer, where the hindering layer has overhangs covering top corners of the hard mask layer; depositing a first barrier layer on the substrate through hindrance of the overhangs, where the first barrier layer covers the hindering layer and a top surface of the first part and exposes the dielectric layer on the sidewall of the opening; and forming a first conductive layer in the opening, where a sidewall of the first conductive layer contacts the dielectric layer.

Abstract: An electrical connector includes an insulating housing and a plurality of terminals coupled to the insulating housing. The insulating housing includes a positioning body, a head portion extending from a first face of the positioning body, and a tail portion extending from a second face of the positioning body. Each terminal includes a first contact portion, a second contact portion, and a retaining portion between the first contact portion and the second contact portion. The retaining portion includes a first coupling portion coupled to the first contact portion and a second coupling portion between the first coupling portion and the second contact portion. The first coupling portion and the second coupling portion are noncoplanar. The first contact portion is coupled to the head portion, the second contact portion is coupled to the tail portion. The retaining portion extends from the head portion to the tail portion.

Abstract: A semiconductor device includes a substrate having a first and second region, a first structure and a second structure. The first structure is formed over the substrate in the first region. The first structure has a first height. The second structure is formed over the substrate in the second region. The second structure has a second height different from the first height.

Abstract: A pixel, a storage capacitor, and a method for forming the same. The storage capacitor formed on a substrate comprises a semiconductor layer, a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer. The semiconductor layer is formed on the substrate wherein the semiconductor layer and the substrate are covered by the first dielectric layer. The first conductive layer is formed on a part of the first dielectric layer. The second dielectric layer is formed on the first conductive layer, and the lateral side of the stacking structure including the second dielectric layer and the first conductive layer has a taper shaped. The second conductive layer is formed on a part of the second dielectric layer.

Abstract: A pixel, a storage capacitor, and a method for forming the same. The storage capacitor formed on a substrate comprises a semiconductor layer, a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer. The semiconductor layer is formed on the substrate wherein the semiconductor layer and the substrate are covered by the first dielectric layer. The first conductive layer is formed on a part of the first dielectric layer. The second dielectric layer is formed on the first conductive layer, and the lateral side of the stacking structure including the second dielectric layer and the first conductive layer has a taper shaped. The second conductive layer is formed on a part of the second dielectric layer.

Abstract: A pixel, a storage capacitor, and a method for forming the same. The storage capacitor formed on a substrate comprises a semiconductor layer, a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer. The semiconductor layer is formed on the substrate wherein the semiconductor layer and the substrate are covered by the first dielectric layer. The first conductive layer is formed on a part of the first dielectric layer. The second dielectric layer is formed on the first conductive layer, and the lateral side of the stacking structure including the second dielectric layer and the first conductive layer has a taper shaped. The second conductive layer is formed on a part of the second dielectric layer.

Abstract: A semiconductor device includes a substrate having a first and second region, a first structure and a second structure. The first structure is formed over the substrate in the first region. The first structure has a first height. The second structure is formed over the substrate in the second region. The second structure has a second height different from the first height.

Abstract: A pixel structure including a scan line, a data line, an active device, a shielding electrode, and a pixel electrode is provided on a substrate. The data line includes an upper conductive wire and a bottom conductive wire. The upper conductive wire is disposed over and across the scan line. The bottom conductive wire is electrically connected to the upper conductive wire. The active device is electrically connected to the scan line and the upper conductive wire. The shielding electrode is disposed over the bottom conductive wire. The pixel electrode disposed over the shielding electrode is electrically connected to the active device. In addition, parts of the pixel electrode and parts of the shielding electrode form a storage capacitor.

Abstract: A pixel structure includes a patterned semiconductor layer disposed on a transistor region of the substrate, a first capacitor electrode disposed on a capacitor region of the substrate, a gate dielectric layer disposed on the first capacitor electrode, a gate disposed on a channel region of the patterned semiconductor layer, a second capacitor electrode, a dielectric layer, and an aluminum capacitor electrode sequentially disposed on the gate dielectric layer of the capacitor region, a first dielectric layer disposed on the gate and the aluminum capacitor electrode, at least one first wire disposed in the first dielectric layer for electrically connecting source/drain region of the patterned semiconductor layer and the aluminum capacitor electrode, a second dielectric layer disposed on the first wire, and a first transparent conductive layer disposed on the second dielectric layer and connected to the first wire.

Abstract: In this pixel structure, a metal layer/a dielectric layer/a heavily doped silicon layer constitutes a bottom electrode/a capacitor dielectric layer/a top electrode of a storage capacitor. At the same time, a metal shielding layer is formed under the thin film transistor to decrease photo-leakage-current.

Abstract: A pixel structure including a scan line, a data line, an active device, a shielding electrode, and a pixel electrode is provided on a substrate. The data line includes an upper conductive wire and a bottom conductive wire. The upper conductive wire is disposed over and across the scan line. The bottom conductive wire is electrically connected to the upper conductive wire. The active device is electrically connected to the scan line and the upper conductive wire. The shielding electrode is disposed over the bottom conductive wire. The pixel electrode disposed over the shielding electrode is electrically connected to the active device. In addition, parts of the pixel electrode and parts of the shielding electrode form a storage capacitor.

Abstract: A pixel structure including a scan line, a data line, an active device, a shielding electrode, and a pixel electrode is provided on a substrate. The data line includes an upper conductive wire and a bottom conductive wire. The upper conductive wire is disposed over and across the scan line. The bottom conductive wire is electrically connected to the upper conductive wire. The active device is electrically connected to the scan line and the upper conductive wire. The shielding electrode is disposed over the bottom conductive wire. The pixel electrode disposed over the shielding electrode is electrically connected to the active device. In addition, parts of the pixel electrode and parts of the shielding electrode form a storage capacitor.

Abstract: A fabrication method of a pixel structure includes providing a substrate. A semiconductor layer and a first conductive layer are formed on the substrate in sequence and patterned to form a semiconductor pattern and a data line pattern. A gate insulation layer and a second conductive layer are formed on the substrate in sequence and patterned to form a gate pattern and a scan line pattern connected to each other. A source region, a drain region, a channel region, and a lightly doped region are formed in the semiconductor pattern. A third conductive layer formed on the substrate is patterned to form a source pattern and a drain pattern. A protective layer is formed on the substrate and patterned to form a contact window to expose the drain pattern. A pixel electrode electrically connected to the drain pattern through the contact window is formed on the protective layer.

Abstract: In this pixel structure, a metal layer/a dielectric layer/a heavily doped silicon layer constitutes a bottom electrode/a capacitor dielectric layer/a top electrode of a storage capacitor. At the same time, a metal shielding layer is formed under the thin film transistor to decrease photo-leakage-current.

Abstract: A pixel structure includes a patterned semiconductor layer disposed on a transistor region of the substrate, a first capacitor electrode disposed on a capacitor region of the substrate, a gate dielectric layer disposed on the first capacitor electrode, a gate disposed on a channel region of the patterned semiconductor layer, a second capacitor electrode, a dielectric layer, and an aluminum capacitor electrode sequentially disposed on the gate dielectric layer of the capacitor region, a first dielectric layer disposed on the gate and the aluminum capacitor electrode, at least one first wire disposed in the first dielectric layer for electrically connecting source/drain region of the patterned semiconductor layer and the aluminum capacitor electrode, a second dielectric layer disposed on the first wire, and a first transparent conductive layer disposed on the second dielectric layer and connected to the first wire.

Abstract: A fabrication method of a pixel structure includes providing a substrate. A semiconductor layer and a first conductive layer are formed on the substrate in sequence and patterned to form a semiconductor pattern and a data line pattern. A gate insulation layer and a second conductive layer are formed on the substrate in sequence and patterned to form a gate pattern and a scan line pattern connected to each other. A source region, a drain region, a channel region, and a lightly doped region are formed in the semiconductor pattern. A third conductive layer formed on the substrate is patterned to form a source pattern and a drain pattern. A protective layer is formed on the substrate and patterned to form a contact window to expose the drain pattern. A pixel electrode electrically connected to the drain pattern through the contact window is formed on the protective layer.

Abstract: In this pixel structure, a metal layer/a dielectric layer/a heavily doped silicon layer constitutes a bottom electrode/a capacitor dielectric layer/a top electrode of a storage capacitor. At the same time, a metal shielding layer is formed under the thin film transistor to decrease photo-leakage-current.